drivers/clock_control: stm32 common fix STM32_SRC_PLLCLK calculation

Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.

This commit resolves this issue for l0, l1.

get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>