Commit 081c9c3b authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Kumar Gala
Browse files

scripts: extract_dts_includes: Generate'_0' defines only when needed 



Indexed defines were systematically generated even when there
was only one element to generate.
So we ended up generated a lot of _0 defines.
Then we needed to generate aliases to these _0 indexed defines,
in order to get useful defines.
For instance:
 #define GPIO_LEDS_0_GPIO_FLAGS_0	4
 #define GPIO_LEDS_0_GPIO_PIN_0		5
 #define GPIO_LEDS_0_GPIO_FLAGS		GPIO_LEDS_0_GPIO_FLAGS_0
 #define GPIO_LEDS_0_GPIO_PIN		GPIO_LEDS_0_GPIO_PIN_0

This commit allows to generate _0 indexed define only if a
property has more than one elements to define.
Aliases generation to _0 indexed defines are also removed.

Note: IRQ are left untouched since this is frequent to handle
multiple IRQs in a driver

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent e099f381

arch/arm/soc/arm/beetle/dts.fixup

+10 −10
Original line number Diff line number Diff line
@@ -3,39 +3,39 @@ 
#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS



/* CMSDK APB Timers */

#define CMSDK_APB_TIMER0			ARM_CMSDK_TIMER_40000000_BASE_ADDRESS_0

#define CMSDK_APB_TIMER0			ARM_CMSDK_TIMER_40000000_BASE_ADDRESS

#define CMSDK_APB_TIMER_0_IRQ			ARM_CMSDK_TIMER_40000000_IRQ_0



#define CMSDK_APB_TIMER1			ARM_CMSDK_TIMER_40001000_BASE_ADDRESS_0

#define CMSDK_APB_TIMER1			ARM_CMSDK_TIMER_40001000_BASE_ADDRESS

#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1	ARM_CMSDK_TIMER_40001000_IRQ_0



/* CMSDK APB Dual Timer */

#define CMSDK_APB_DTIMER			ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS_0

#define CMSDK_APB_DTIMER			ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS

#define CMSDK_APB_DUALTIMER_IRQ			ARM_CMSDK_DTIMER_40002000_IRQ_0



/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */

#define CMSDK_APB_UART0				ARM_CMSDK_UART_40004000_BASE_ADDRESS_0

#define CMSDK_APB_UART0				ARM_CMSDK_UART_40004000_BASE_ADDRESS

#define CMSDK_APB_UART_0_IRQ			ARM_CMSDK_UART_40004000_IRQ_0

#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI	ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY

#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE	ARM_CMSDK_UART_40004000_CURRENT_SPEED

#define CONFIG_UART_CMSDK_APB_PORT0_NAME	ARM_CMSDK_UART_40004000_LABEL



#define CMSDK_APB_UART1				ARM_CMSDK_UART_40005000_BASE_ADDRESS_0

#define CMSDK_APB_UART1				ARM_CMSDK_UART_40005000_BASE_ADDRESS

#define CMSDK_APB_UART_1_IRQ			ARM_CMSDK_UART_40005000_IRQ_0

#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI	ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY

#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE	ARM_CMSDK_UART_40005000_CURRENT_SPEED

#define CONFIG_UART_CMSDK_APB_PORT1_NAME	ARM_CMSDK_UART_40005000_LABEL



/* CMSDK APB Watchdog */

#define CMSDK_APB_WDOG				ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS_0

#define CMSDK_APB_WDOG				ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS



/* CMSDK AHB General Purpose Input/Output (GPIO) */

#define CMSDK_AHB_GPIO0				ARM_CMSDK_GPIO_40010000_BASE_ADDRESS_0

#define CMSDK_AHB_GPIO0				ARM_CMSDK_GPIO_40010000_BASE_ADDRESS



#define CMSDK_AHB_GPIO1				ARM_CMSDK_GPIO_40011000_BASE_ADDRESS_0

#define CMSDK_AHB_GPIO1				ARM_CMSDK_GPIO_40011000_BASE_ADDRESS



#define CMSDK_AHB_GPIO2				ARM_CMSDK_GPIO_40012000_BASE_ADDRESS_0

#define CMSDK_AHB_GPIO2				ARM_CMSDK_GPIO_40012000_BASE_ADDRESS



#define CMSDK_AHB_GPIO3				ARM_CMSDK_GPIO_40013000_BASE_ADDRESS_0

#define CMSDK_AHB_GPIO3				ARM_CMSDK_GPIO_40013000_BASE_ADDRESS



/* End of SoC Level DTS fixup file */

arch/arm/soc/atmel_sam/same70/dts.fixup

+2 −2
Original line number Diff line number Diff line
@@ -91,12 +91,12 @@ 
#define CONFIG_USART_SAM_PORT_2_IRQ_PRIO	ATMEL_SAM_USART_4002C000_IRQ_0_PRIORITY

#define CONFIG_USART_SAM_PORT_2_PERIPHERAL_ID	ATMEL_SAM_USART_4002C000_PERIPHERAL_ID



#define CONFIG_ADC_0_BASE_ADDRESS	ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS_0

#define CONFIG_ADC_0_BASE_ADDRESS	ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS

#define CONFIG_ADC_0_IRQ	ATMEL_SAM_AFEC_4003C000_IRQ_0

#define CONFIG_ADC_0_IRQ_PRI	ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY

#define CONFIG_ADC_0_NAME	ATMEL_SAM_AFEC_4003C000_LABEL



#define CONFIG_ADC_1_BASE_ADDRESS	ATMEL_SAM_AFEC_40064000_BASE_ADDRESS_0

#define CONFIG_ADC_1_BASE_ADDRESS	ATMEL_SAM_AFEC_40064000_BASE_ADDRESS

#define CONFIG_ADC_1_IRQ	ATMEL_SAM_AFEC_40064000_IRQ_0

#define CONFIG_ADC_1_IRQ_PRI	ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY

#define CONFIG_ADC_1_NAME	ATMEL_SAM_AFEC_40064000_LABEL

arch/arm/soc/atmel_sam0/samd21/dts.fixup

+1 −1
Original line number Diff line number Diff line 
/* SoC level DTS fixup file */



#define FLASH_DEV_BASE_ADDRESS		ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS_0

#define FLASH_DEV_BASE_ADDRESS		ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS

#define FLASH_DEV_NAME			ATMEL_SAM0_NVMCTRL_41004000_LABEL



#define CONFIG_GPIO_SAM0_PORTA_LABEL ATMEL_SAM0_GPIO_41004400_LABEL

arch/arm/soc/nordic_nrf/nrf51/dts.fixup

+2 −2
Original line number Diff line number Diff line
@@ -7,13 +7,13 @@ 


#define FLASH_DEV_NAME			NRF_NRF51_FLASH_CONTROLLER_4001E000_LABEL



#define CONFIG_I2C_0_BASE_ADDR		NORDIC_NRF5_I2C_40003000_BASE_ADDRESS_0

#define CONFIG_I2C_0_BASE_ADDR		NORDIC_NRF5_I2C_40003000_BASE_ADDRESS

#define CONFIG_I2C_0_NAME		NORDIC_NRF5_I2C_40003000_LABEL

#define CONFIG_I2C_0_BITRATE		NORDIC_NRF5_I2C_40003000_CLOCK_FREQUENCY

#define CONFIG_I2C_0_IRQ_PRI		NORDIC_NRF5_I2C_40003000_IRQ_0_PRIORITY

#define CONFIG_I2C_0_IRQ		NORDIC_NRF5_I2C_40003000_IRQ_0



#define CONFIG_I2C_1_BASE_ADDR		NORDIC_NRF5_I2C_40004000_BASE_ADDRESS_0

#define CONFIG_I2C_1_BASE_ADDR		NORDIC_NRF5_I2C_40004000_BASE_ADDRESS

#define CONFIG_I2C_1_NAME		NORDIC_NRF5_I2C_40004000_LABEL

#define CONFIG_I2C_1_BITRATE		NORDIC_NRF5_I2C_40004000_CLOCK_FREQUENCY

#define CONFIG_I2C_1_IRQ_PRI		NORDIC_NRF5_I2C_40004000_IRQ_0_PRIORITY

arch/arm/soc/nordic_nrf/nrf52/dts.fixup

+2 −2
Original line number Diff line number Diff line
@@ -7,13 +7,13 @@ 


#define FLASH_DEV_NAME			NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL



#define CONFIG_I2C_0_BASE_ADDR		NORDIC_NRF5_I2C_40003000_BASE_ADDRESS_0

#define CONFIG_I2C_0_BASE_ADDR		NORDIC_NRF5_I2C_40003000_BASE_ADDRESS

#define CONFIG_I2C_0_NAME		NORDIC_NRF5_I2C_40003000_LABEL

#define CONFIG_I2C_0_BITRATE		NORDIC_NRF5_I2C_40003000_CLOCK_FREQUENCY

#define CONFIG_I2C_0_IRQ_PRI		NORDIC_NRF5_I2C_40003000_IRQ_0_PRIORITY

#define CONFIG_I2C_0_IRQ		NORDIC_NRF5_I2C_40003000_IRQ_0



#define CONFIG_I2C_1_BASE_ADDR		NORDIC_NRF5_I2C_40004000_BASE_ADDRESS_0

#define CONFIG_I2C_1_BASE_ADDR		NORDIC_NRF5_I2C_40004000_BASE_ADDRESS

#define CONFIG_I2C_1_NAME		NORDIC_NRF5_I2C_40004000_LABEL

#define CONFIG_I2C_1_BITRATE		NORDIC_NRF5_I2C_40004000_CLOCK_FREQUENCY

#define CONFIG_I2C_1_IRQ_PRI		NORDIC_NRF5_I2C_40004000_IRQ_0_PRIORITY

CRA Git | Maintained and supported by SUSTech CRA and CCSE