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Commit 069d409b authored by Aurelien Jarno's avatar Aurelien Jarno Committed by Anas Nashif
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arch: arm: stm32: enable instruction and data caches on STM32F7 



The Cortex-M7 CPU included in the STM32F7 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization. Note that the D-cache should only be enabled if it
is disabled, to workaround CMSIS issue #331.

Signed-off-by: default avatarAurelien Jarno <aurelien@aurel32.net>
parent 9039d6fd
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