boards: arm: stm32: nucleo_h563zi enable can

Enable the FDCAN1 using pll1_q as clock source on pins TX/RX PD1/PD0.

Using 160MHz pll1_q output with an additional can clk-divider, to allow
other peripheral to use such a high clock source and to increase test
coverage.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>