boards: nucleo_h563zi: change pll1 pllq frequency to 160MHz

In preparation for CAN support, this commit changes the q divier of PLL1
from 2 to 3 to result in a output frequency of 160MHz.
Using a can clk-divider of 2 a 80MHz Core clock frequency can be configured
which is recommended for can bit rates over 2MHz for good interoperability
between nodes.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>