Commit 03684e85 authored by Mike J. Chen's avatar Mike J. Chen Committed by Fabio Baltieri
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drivers: spi: mcux_flexcomm: make async mode with dma work



The current driver implementation would block even when the async
API was invoked, so it wasn't really async.

This CL also fully chains the DMA transfer using multiple dma blocks
and makes the number of dma blocks available a config value. The
increase in number of dma blocks is needed so that a spi_buf_set
that has many entries can be converted into chained dma transfers
with the last transfer in a separate block that will set the EOT flag.

Also make some improvements:
1) When doing single cnt transfer, don't use the SDK driver but
   use a new fucntion spi_mcux_transfer_single_word().
   It's much more efficient and does not use an ISR
   like the SDK function does just to send one word.

2) Fix calls to spi_context_update_tx/rx() so that the
   correct word size is passed in, instead of previously
   being hardcoded to 1. This only matters when word size
   is two. Evaluate the word_size_bytes and word_size_bits
   once and store the values in data instead of computing
   it multiple times in various parts of the driver

3) When CONFIG_SPI_MCUX_FLEXCOMM_DMA is defined, we
   do not use the IRQ handler, so add #ifdefs to compile
   that code out. This reduces code size.

Signed-off-by: default avatarMike J. Chen <mjchen@google.com>
parent 0c1e9c3e
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+14 −0
Original line number Diff line number Diff line
@@ -18,4 +18,18 @@ config SPI_MCUX_FLEXCOMM_DMA
	help
	  Enable the SPI DMA mode for SPI instances
	  that enable dma channels in their device tree node.

config SPI_MCUX_FLEXCOMM_DMA_MAX_BLOCKS
	int "MCUX FLEXCOMM SPI DMA Blocks Available"
	range 2 100
	depends on SPI_MCUX_FLEXCOMM_DMA
	default 6
	help
	  Specifies the number of DMA blocks available for SPI transfer. Enough
	  DMA blocks must be configured to handle all of the buffers in the
	  transfer buffer set. If tx and rx buffers are not the same size, an
	  additional block is needed for each set. A separate block is needed
	  for the last word so that a final one word buffer can be used to set the
	  end of transfer bit which will release the CS.

endif # SPI_MCUX_FLEXCOMM
+272 −264

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