tests: drivers: spi: spi_loopback: Update slow rates for MAX32 boards

The requested SPI clock rate and the actual rate that is set can be
different depending on the peripheral clock and divisors available to
the SPI peripheral. For some MAX32 SoCs, actual rate ended up being
higher than the devicetree setting. This would then cause latency tests
to fail as transfers finish earlier than minimum expected duration.

Update the test frequency values in several MAX32 board overlays to pass
latency tests.

Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
(cherry picked from commit 3de5883f)