Commit ff54ecb0 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
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drm/amd/display: Add Renoir clock registers list 



These are the registers used to program the clock hw.

Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b593bce5

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

+17 −0
Original line number Diff line number Diff line
@@ -78,6 +78,23 @@ 
		SRII(PIXEL_RATE_CNTL, OTG, 5)

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN2_1)

#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \

		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

		SRII(PHASE, DP_DTO, 0),\

		SRII(PHASE, DP_DTO, 1),\

		SRII(PHASE, DP_DTO, 2),\

		SRII(PHASE, DP_DTO, 3),\

		SRII(MODULO, DP_DTO, 0),\

		SRII(MODULO, DP_DTO, 1),\

		SRII(MODULO, DP_DTO, 2),\

		SRII(MODULO, DP_DTO, 3),\

		SRII(PIXEL_RATE_CNTL, OTG, 0),\

		SRII(PIXEL_RATE_CNTL, OTG, 1),\

		SRII(PIXEL_RATE_CNTL, OTG, 2),\

		SRII(PIXEL_RATE_CNTL, OTG, 3)

#endif



#if defined(CONFIG_DRM_AMD_DC_DCN2_0)

#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\

	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\

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