Commit b593bce5 authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
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drm/amd/display: Add Renoir registers (v3) 



add registers for dcn, clk, and renoir ip offsets

v2: header cleanup (Alex)
v3: Add DPCS registers (Hersen)

Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eee3258e

drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h

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/*

 * Copyright (C) 2019  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _clk_10_0_2_OFFSET_HEADER

#define _clk_10_0_2_OFFSET_HEADER







// addressBlock: clk_clk1_0_SmuClkDec

// base address: 0x5b800

#define mmCLK1_CLK_PLL_REQ                                                                             0x000f

#define mmCLK1_CLK_PLL_REQ_BASE_IDX                                                                    1

#define mmCLK1_CLK0_BYPASS_CNTL                                                                        0x0049

#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                               1

#define mmCLK1_CLK1_BYPASS_CNTL                                                                        0x0053

#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                               1

#define mmCLK1_CLK2_BYPASS_CNTL                                                                        0x005d

#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                               1

#define mmCLK1_CLK2_STATUS                                                                             0x005e

#define mmCLK1_CLK2_STATUS_BASE_IDX                                                                    1

#define mmCLK1_CLK3_DFS_CNTL                                                                           0x005f

#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX                                                                  1

#define mmCLK1_CLK3_DS_CNTL                                                                            0x0060

#define mmCLK1_CLK3_DS_CNTL_BASE_IDX                                                                   1

#define mmCLK1_CLK3_ALLOW_DS                                                                           0x0061

#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX                                                                  1

#define mmCLK1_CLK3_BYPASS_CNTL                                                                        0x0067

#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                               1

#define mmCLK1_CLK0_CURRENT_CNT                                                                        0x008a

#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX                                                               1

#define mmCLK1_CLK1_CURRENT_CNT                                                                        0x008b

#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX                                                               1

#define mmCLK1_CLK2_CURRENT_CNT                                                                        0x008c

#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX                                                               1

#define mmCLK1_CLK3_CURRENT_CNT                                                                        0x008d

#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX                                                               1





#endif

drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h

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/*

 * Copyright (C) 2019  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef _clk_10_0_2_SH_MASK_HEADER

#define _clk_10_0_2_SH_MASK_HEADER





// addressBlock: clk_clk1_0_SmuClkDec

//CLK1_CLK_PLL_REQ

#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0

#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc

#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10

#define CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL

#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L

#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L

//CLK1_CLK0_BYPASS_CNTL

#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0

#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                         0x10

#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L

#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                           0x000F0000L

//CLK1_CLK1_BYPASS_CNTL

#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0

#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                         0x10

#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L

#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                           0x000F0000L

//CLK1_CLK2_BYPASS_CNTL

#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0

#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                         0x10

#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L

#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                           0x000F0000L

//CLK1_CLK3_DS_CNTL

#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0

#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x00000007L

//CLK1_CLK3_ALLOW_DS

#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                              0x0

#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                                0x00000001L

//CLK1_CLK3_BYPASS_CNTL

#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0

#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                         0x10

#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L

#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                           0x000F0000L

//CLK1_CLK0_CURRENT_CNT

#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0

#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL

//CLK1_CLK1_CURRENT_CNT

#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0

#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL

//CLK1_CLK2_CURRENT_CNT

#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0

#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL

//CLK1_CLK3_CURRENT_CNT

#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0

#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL





#endif

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h

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drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h

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drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h

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