Commit ff060019 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... 

Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next

 - Support for STM32F769
 - Rework AT91 sckc DT bindings
 - Fix slow RC oscillator issue on sama5d3
 - AT91 sam9x60 PMC support
 - SiFive FU540 PRCI and PLL support

* clk-stm32f4:
  clk: stm32mp1: Add ddrperfm clock
  clk: stm32: Introduce clocks of STM32F769 board

* clk-tegra:
  clk: tegra: divider: Mark Memory Controller clock as read-only
  clk: tegra: emc: Replace BUG() with WARN_ONCE()
  clk: tegra: emc: Fix EMC max-rate clamping
  clk: tegra: emc: Support multiple RAM codes
  clk: tegra: emc: Don't enable EMC clock manually
  clk: tegra124: Remove lock-enable bit from PLLM
  clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
  clk: tegra: Don't enable already enabled PLLs

* clk-at91:
  clk: at91: Mark struct clk_range as const
  clk: at91: add sam9x60 pmc driver
  dt-bindings: clk: at91: add bindings for SAM9X60 pmc
  clk: at91: add sam9x60 PLL driver
  clk: at91: master: Add sam9x60 support
  clk: at91: usb: Add sam9x60 support
  clk: at91: allow configuring generated PCR layout
  clk: at91: allow configuring peripheral PCR layout
  clk: at91: sckc: handle different RC startup time
  clk: at91: modernize sckc binding
  dt-bindings: clock: at91: new sckc bindings

* clk-sifive-fu540:
  clk: sifive: add a driver for the SiFive FU540 PRCI IP block
  clk: analogbits: add Wide-Range PLL library
  dt-bindings: clk: add documentation for the SiFive PRCI driver

* clk-spdx:
  clk: sunxi-ng: Use the correct style for SPDX License Identifier
  clk: sprd: Use the correct style for SPDX License Identifier
  clk: renesas: Use the correct style for SPDX License Identifier
  clk: qcom: Use the correct style for SPDX License Identifier
  clk: davinci: Use the correct style for SPDX License Identifier
  clk: actions: Use the correct style for SPDX License Identifier
parents 5816b745 b06df56b e71f4d38 7b4c162e 30b8e27e d65530ca

Documentation/devicetree/bindings/clock/at91-clock.txt

+14 −19
Original line number Diff line number Diff line
@@ -8,35 +8,30 @@ Slow Clock controller: 


Required properties:

- compatible : shall be one of the following:

	"atmel,at91sam9x5-sckc" or

	"atmel,at91sam9x5-sckc",

	"atmel,sama5d3-sckc" or

	"atmel,sama5d4-sckc":

		at91 SCKC (Slow Clock Controller)

		This node contains the slow clock definitions.



	"atmel,at91sam9x5-clk-slow-osc":

		at91 slow oscillator



	"atmel,at91sam9x5-clk-slow-rc-osc":

		at91 internal slow RC oscillator

- reg : defines the IO memory reserved for the SCKC.

- #size-cells : shall be 0 (reg is used to encode clk id).

- #address-cells : shall be 1 (reg is used to encode clk id).

- #clock-cells : shall be 0.

- clocks : shall be the input parent clock phandle for the clock.



Optional properties:

- atmel,osc-bypass : boolean property. Set this when a clock signal is directly

  provided on XIN.



For example:

	sckc: sckc@fffffe50 {

		compatible = "atmel,sama5d3-pmc";

		reg = <0xfffffe50 0x4>

		#size-cells = <0>;

		#address-cells = <1>;



		/* put at91 slow clocks here */

	sckc@fffffe50 {

		compatible = "atmel,at91sam9x5-sckc";

		reg = <0xfffffe50 0x4>;

		clocks = <&slow_xtal>;

		#clock-cells = <0>;

	};



Power Management Controller (PMC):



Required properties:

- compatible : shall be "atmel,<chip>-pmc", "syscon":

- compatible : shall be "atmel,<chip>-pmc", "syscon" or

	"microchip,sam9x60-pmc"

	<chip> can be: at91rm9200, at91sam9260, at91sam9261,

	at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,

	at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,

Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt

0 → 100644
+46 −0
Original line number Diff line number Diff line 
SiFive FU540 PRCI bindings



On the FU540 family of SoCs, most system-wide clock and reset integration

is via the PRCI IP block.



Required properties:

- compatible: Should be "sifive,<chip>-prci".  Only one value is

	supported: "sifive,fu540-c000-prci"

- reg: Should describe the PRCI's register target physical address region

- clocks: Should point to the hfclk device tree node and the rtcclk

          device tree node.  The RTC clock here is not a time-of-day clock,

	  but is instead a high-stability clock source for system timers

	  and cycle counters.

- #clock-cells: Should be <1>



The clock consumer should specify the desired clock via the clock ID

macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.

These macros begin with PRCI_CLK_.



The hfclk and rtcclk nodes are required, and represent physical

crystals or resonators located on the PCB.  These nodes should be present

underneath /, rather than /soc.



Examples:



/* under /, in PCB-specific DT data */

hfclk: hfclk {

	#clock-cells = <0>;

	compatible = "fixed-clock";

	clock-frequency = <33333333>;

	clock-output-names = "hfclk";

};

rtcclk: rtcclk {

	#clock-cells = <0>;

	compatible = "fixed-clock";

	clock-frequency = <1000000>;

	clock-output-names = "rtcclk";

};



/* under /soc, in SoC-specific DT data */

prci: clock-controller@10000000 {

	compatible = "sifive,fu540-c000-prci";

	reg = <0x0 0x10000000 0x0 0x1000>;

	clocks = <&hfclk>, <&rtcclk>;

	#clock-cells = <1>;

};

Documentation/devicetree/bindings/clock/st,stm32-rcc.txt

+6 −0
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ Required properties: 
  "st,stm32f42xx-rcc"

  "st,stm32f469-rcc"

  "st,stm32f746-rcc"

  "st,stm32f769-rcc"



- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below
@@ -102,6 +104,10 @@ The secondary index is bound with the following magic numbers: 
	28	CLK_I2C3

	29	CLK_I2C4

	30	CLK_LPTIMER	(LPTimer1 clock)

	31	CLK_PLL_SRC

	32	CLK_DFSDM1

	33	CLK_ADFSDM1

	34	CLK_F769_DSI

)



Example:

MAINTAINERS

+6 −0
Original line number Diff line number Diff line
@@ -960,6 +960,12 @@ F: drivers/iio/adc/ltc2497* 
X:	drivers/iio/*/adjd*

F:	drivers/staging/iio/*/ad*



ANALOGBITS PLL LIBRARIES

M:	Paul Walmsley <paul.walmsley@sifive.com>

S:	Supported

F:	drivers/clk/analogbits/*

F:	include/linux/clk/analogbits*



ANDES ARCHITECTURE

M:	Greentime Hu <green.hu@gmail.com>

M:	Vincent Chen <deanbo422@gmail.com>

drivers/clk/Kconfig

+3 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0



config CLKDEV_LOOKUP

	bool
@@ -304,6 +305,7 @@ config COMMON_CLK_FIXED_MMIO 
	  Support for Memory Mapped IO Fixed clocks



source "drivers/clk/actions/Kconfig"

source "drivers/clk/analogbits/Kconfig"

source "drivers/clk/bcm/Kconfig"

source "drivers/clk/hisilicon/Kconfig"

source "drivers/clk/imgtec/Kconfig"
@@ -316,6 +318,7 @@ source "drivers/clk/mvebu/Kconfig" 
source "drivers/clk/qcom/Kconfig"

source "drivers/clk/renesas/Kconfig"

source "drivers/clk/samsung/Kconfig"

source "drivers/clk/sifive/Kconfig"

source "drivers/clk/sprd/Kconfig"

source "drivers/clk/sunxi/Kconfig"

source "drivers/clk/sunxi-ng/Kconfig"

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