Commit e71f4d38 authored Apr 14, 2019 by Dmitry Osipenko Committed by Stephen Boyd Apr 25, 2019

clk: tegra: divider: Mark Memory Controller clock as read-only

The Memory Controller (MC) clock rate can't be simply changed and nothing
in kernel need to change the rate, hence let's make the clock read-only.
This id also needed for the EMC driver because timing configuration may
require the MC clock diver to be disabled, that is handled by the EMC
clock / EMC driver integration and CLK framework shall not touch the
MC divider configuration on the EMC clock rate change.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent f4037654

drivers/clk/tegra/clk-divider.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -175,6 +175,7 @@ struct clk tegra_clk_register_mc(const char name, const char *parent_name,
		void __iomem reg, spinlock_t lock)
		{
		return clk_register_divider_table(NULL, name, parent_name,
		CLK_IS_CRITICAL, reg, 16, 1, 0,
		CLK_IS_CRITICAL,
		reg, 16, 1, CLK_DIVIDER_READ_ONLY,
		mc_div_table, lock);
		}

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