Commit fcd65353 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Will Deacon
Browse files

arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register 



Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX,
SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-9-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 0ae43a99

arch/arm64/include/asm/sysreg.h

+8 −0
Original line number Diff line number Diff line
@@ -794,6 +794,14 @@ 
#define ID_ISAR6_DP_SHIFT		4

#define ID_ISAR6_JSCVT_SHIFT		0



#define ID_MMFR4_EVT_SHIFT		28

#define ID_MMFR4_CCIDX_SHIFT		24

#define ID_MMFR4_LSM_SHIFT		20

#define ID_MMFR4_HPDS_SHIFT		16

#define ID_MMFR4_CNP_SHIFT		12

#define ID_MMFR4_XNX_SHIFT		8

#define ID_MMFR4_SPECSEI_SHIFT		0



#define ID_MMFR5_ETS_SHIFT		0



#define ID_PFR0_DIT_SHIFT		24

arch/arm64/kernel/cpufeature.c

+13 −0
Original line number Diff line number Diff line
@@ -392,7 +392,20 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = { 
};



static const struct arm64_ftr_bits ftr_id_mmfr4[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),	/* ac2 */

	/*

	 * SpecSEI = 1 indicates that the PE might generate an SError on an

	 * external abort on speculative read. It is safe to assume that an

	 * SError might be generated than it will not be. Hence it has been

	 * classified as FTR_HIGHER_SAFE.

	 */

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),

	ARM64_FTR_END,

};

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