Commit 0ae43a99 authored May 19, 2020 by Anshuman Khandual Committed by Will Deacon May 21, 2020

arm64/cpufeature: Add remaining feature bits in ID_PFR0 register



Enable DIT and CSV2 feature bits in ID_PFR0 register as per ARM DDI 0487F.a
specification. Except RAS and AMU, all other feature bits are now enabled.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-8-git-send-email-anshuman.khandual@arm.com


Signed-off-by: Will Deacon <will@kernel.org>

parent 152accf8

arch/arm64/include/asm/sysreg.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -796,6 +796,9 @@

		#define ID_MMFR5_ETS_SHIFT 0

		#define ID_PFR0_DIT_SHIFT 24
		#define ID_PFR0_CSV2_SHIFT 16

		#define ID_PFR2_SSBS_SHIFT 4
		#define ID_PFR2_CSV3_SHIFT 0

arch/arm64/kernel/cpufeature.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -425,6 +425,8 @@ static const struct arm64_ftr_bits ftr_id_isar6[] = {
		};

		static const struct arm64_ftr_bits ftr_id_pfr0[] = {
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
		ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */

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