Commit 152accf8 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Will Deacon
Browse files

arm64/cpufeature: Introduce ID_MMFR5 CPU register 



This adds basic building blocks required for ID_MMFR5 CPU register which
provides information about the implemented memory model and memory
management support in AArch32 state. This is added per ARM DDI 0487F.a
specification.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1589881254-10082-7-git-send-email-anshuman.khandual@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent dd35ec07

arch/arm64/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ struct cpuinfo_arm64 { 
	u32		reg_id_mmfr1;

	u32		reg_id_mmfr2;

	u32		reg_id_mmfr3;

	u32		reg_id_mmfr5;

	u32		reg_id_pfr0;

	u32		reg_id_pfr1;

	u32		reg_id_pfr2;

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ 
#define SYS_ID_MMFR2_EL1		sys_reg(3, 0, 0, 1, 6)

#define SYS_ID_MMFR3_EL1		sys_reg(3, 0, 0, 1, 7)

#define SYS_ID_MMFR4_EL1		sys_reg(3, 0, 0, 2, 6)

#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)



#define SYS_ID_ISAR0_EL1		sys_reg(3, 0, 0, 2, 0)

#define SYS_ID_ISAR1_EL1		sys_reg(3, 0, 0, 2, 1)
@@ -793,6 +794,8 @@ 
#define ID_ISAR6_DP_SHIFT		4

#define ID_ISAR6_JSCVT_SHIFT		0



#define ID_MMFR5_ETS_SHIFT		0



#define ID_PFR2_SSBS_SHIFT		4

#define ID_PFR2_CSV3_SHIFT		0

arch/arm64/kernel/cpufeature.c

+10 −0
Original line number Diff line number Diff line
@@ -408,6 +408,11 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = { 
	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_mmfr5[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),

	ARM64_FTR_END,

};



static const struct arm64_ftr_bits ftr_id_isar6[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
@@ -533,6 +538,7 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),

	ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),

	ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),

	ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),



	/* Op1 = 0, CRn = 0, CRm = 4 */

	ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
@@ -738,6 +744,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) 
		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);

		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);

		init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);

		init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);

		init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);

		init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);

		init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
@@ -872,6 +879,8 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 
				      info->reg_id_mmfr2, boot->reg_id_mmfr2);

	taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,

				      info->reg_id_mmfr3, boot->reg_id_mmfr3);

	taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,

				      info->reg_id_mmfr5, boot->reg_id_mmfr5);

	taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,

				      info->reg_id_pfr0, boot->reg_id_pfr0);

	taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
@@ -1012,6 +1021,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) 
	read_sysreg_case(SYS_ID_MMFR1_EL1);

	read_sysreg_case(SYS_ID_MMFR2_EL1);

	read_sysreg_case(SYS_ID_MMFR3_EL1);

	read_sysreg_case(SYS_ID_MMFR5_EL1);

	read_sysreg_case(SYS_ID_ISAR0_EL1);

	read_sysreg_case(SYS_ID_ISAR1_EL1);

	read_sysreg_case(SYS_ID_ISAR2_EL1);

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -374,6 +374,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 
		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);

		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);

		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);

		info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);

		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);

		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);

		info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);

arch/arm64/kvm/sys_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -1458,7 +1458,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { 
	ID_UNALLOCATED(3,3),

	ID_SANITISED(ID_PFR2_EL1),

	ID_HIDDEN(ID_DFR1_EL1),

	ID_UNALLOCATED(3,6),

	ID_SANITISED(ID_MMFR5_EL1),

	ID_UNALLOCATED(3,7),



	/* AArch64 ID registers */

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