Commit fc3b1550 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs 



The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.

Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).

Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarSuman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
parent a323da4b

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

+45 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
/dts-v1/;



#include "k3-j7200-som-p0.dtsi"

#include <dt-bindings/net/ti-dp83867.h>



/ {

	chosen {
@@ -14,6 +15,32 @@ 
	};

};



&wkup_pmx0 {

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */

			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */

			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */

			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */

			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */

			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */

			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */

			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */

			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */

			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */

			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */

			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */

		>;

	};



	mcu_mdio_pins_default: mcu-mdio1-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */

			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */

		>;

	};

};



&wkup_uart0 {

	/* Wakeup UART is used by System firmware */

	status = "disabled";
@@ -63,3 +90,21 @@ 
	/* UART not brought out */

	status = "disabled";

};



&mcu_cpsw {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

};



&davinci_mdio {

	phy0: ethernet-phy@0 {

		reg = <0>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

	};

};



&cpsw_port1 {

	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};

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