Merge tag 'imx-soc-4.4' of... (fa54cda7) · Commits · 戴 / test

arch/arm/mach-imx/common.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -131,6 +131,7 @@ void imx6q_pm_init(void);
		void imx6dl_pm_init(void);
		void imx6sl_pm_init(void);
		void imx6sx_pm_init(void);
		void imx6ul_pm_init(void);

		#ifdef CONFIG_PM
		void imx51_pm_init(void);

arch/arm/mach-imx/mach-imx6ul.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -67,6 +67,7 @@ static void __init imx6ul_init_machine(void)
		of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
		imx6ul_enet_init();
		imx_anatop_init();
		imx6ul_pm_init();
		}

		static void __init imx6ul_init_irq(void)
		@@ -74,6 +75,13 @@ static void __init imx6ul_init_irq(void)
		imx_init_revision_from_anatop();
		imx_src_init();
		irqchip_init();
		imx6_pm_ccm_init("fsl,imx6ul-ccm");
		}

		static void __init imx6ul_init_late(void)
		{
		if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
		platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
		}

		static const char *imx6ul_dt_compat[] __initconst = {
		@@ -84,5 +92,6 @@ static const char *imx6ul_dt_compat[] __initconst = {
		DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
		.init_irq = imx6ul_init_irq,
		.init_machine = imx6ul_init_machine,
		.init_late = imx6ul_init_late,
		.dt_compat = imx6ul_dt_compat,
		MACHINE_END

arch/arm/mach-imx/mach-imx7d.c

+74 −0

Original line number	Diff line number	Diff line
		@@ -6,12 +6,85 @@
		* published by the Free Software Foundation.
		*/
		#include <linux/irqchip.h>
		#include <linux/mfd/syscon.h>
		#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
		#include <linux/of_platform.h>
		#include <linux/phy.h>
		#include <linux/regmap.h>

		#include <asm/mach/arch.h>
		#include <asm/mach/map.h>

		#include "common.h"

		static int ar8031_phy_fixup(struct phy_device *dev)
		{
		u16 val;

		/* Set RGMII IO voltage to 1.8V */
		phy_write(dev, 0x1d, 0x1f);
		phy_write(dev, 0x1e, 0x8);

		/* disable phy AR8031 SmartEEE function. */
		phy_write(dev, 0xd, 0x3);
		phy_write(dev, 0xe, 0x805d);
		phy_write(dev, 0xd, 0x4003);
		val = phy_read(dev, 0xe);
		val &= ~(0x1 << 8);
		phy_write(dev, 0xe, val);

		/* introduce tx clock delay */
		phy_write(dev, 0x1d, 0x5);
		val = phy_read(dev, 0x1e);
		val \|= 0x0100;
		phy_write(dev, 0x1e, val);

		return 0;
		}

		static int bcm54220_phy_fixup(struct phy_device *dev)
		{
		/* enable RXC skew select RGMII copper mode */
		phy_write(dev, 0x1e, 0x21);
		phy_write(dev, 0x1f, 0x7ea8);
		phy_write(dev, 0x1e, 0x2f);
		phy_write(dev, 0x1f, 0x71b7);

		return 0;
		}

		#define PHY_ID_AR8031 0x004dd074
		#define PHY_ID_BCM54220 0x600d8589

		static void __init imx7d_enet_phy_init(void)
		{
		if (IS_BUILTIN(CONFIG_PHYLIB)) {
		phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
		ar8031_phy_fixup);
		phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
		bcm54220_phy_fixup);
		}
		}

		static void __init imx7d_enet_clk_sel(void)
		{
		struct regmap *gpr;

		gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
		if (!IS_ERR(gpr)) {
		regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
		regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
		} else {
		pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
		}
		}

		static inline void imx7d_enet_init(void)
		{
		imx7d_enet_phy_init();
		imx7d_enet_clk_sel();
		}

		static void __init imx7d_init_machine(void)
		{
		struct device *parent;
		@@ -22,6 +95,7 @@ static void __init imx7d_init_machine(void)

		of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
		imx_anatop_init();
		imx7d_enet_init();
		}

		static void __init imx7d_init_irq(void)

arch/arm/mach-imx/pm-imx6.c

+40 −6

Original line number	Diff line number	Diff line
		@@ -93,6 +93,7 @@ struct imx6_pm_socdata {
		const char *src_compat;
		const char *iomuxc_compat;
		const char *gpc_compat;
		const char *pl310_compat;
		const u32 mmdc_io_num;
		const u32 *mmdc_io_offset;
		};
		@@ -137,11 +138,19 @@ static const u32 imx6sx_mmdc_io_offset[] __initconst = {
		0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
		};

		static const u32 imx6ul_mmdc_io_offset[] __initconst = {
		0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */
		0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */
		0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */
		0x494, 0x4b0, /* MODE_CTL, MODE, */
		};

		static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
		.mmdc_compat = "fsl,imx6q-mmdc",
		.src_compat = "fsl,imx6q-src",
		.iomuxc_compat = "fsl,imx6q-iomuxc",
		.gpc_compat = "fsl,imx6q-gpc",
		.pl310_compat = "arm,pl310-cache",
		.mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
		.mmdc_io_offset = imx6q_mmdc_io_offset,
		};
		@@ -151,6 +160,7 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
		.src_compat = "fsl,imx6q-src",
		.iomuxc_compat = "fsl,imx6dl-iomuxc",
		.gpc_compat = "fsl,imx6q-gpc",
		.pl310_compat = "arm,pl310-cache",
		.mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
		.mmdc_io_offset = imx6dl_mmdc_io_offset,
		};
		@@ -160,6 +170,7 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
		.src_compat = "fsl,imx6sl-src",
		.iomuxc_compat = "fsl,imx6sl-iomuxc",
		.gpc_compat = "fsl,imx6sl-gpc",
		.pl310_compat = "arm,pl310-cache",
		.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
		.mmdc_io_offset = imx6sl_mmdc_io_offset,
		};
		@@ -169,10 +180,21 @@ static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
		.src_compat = "fsl,imx6sx-src",
		.iomuxc_compat = "fsl,imx6sx-iomuxc",
		.gpc_compat = "fsl,imx6sx-gpc",
		.pl310_compat = "arm,pl310-cache",
		.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
		.mmdc_io_offset = imx6sx_mmdc_io_offset,
		};

		static const struct imx6_pm_socdata imx6ul_pm_data __initconst = {
		.mmdc_compat = "fsl,imx6ul-mmdc",
		.src_compat = "fsl,imx6ul-src",
		.iomuxc_compat = "fsl,imx6ul-iomuxc",
		.gpc_compat = "fsl,imx6ul-gpc",
		.pl310_compat = NULL,
		.mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset),
		.mmdc_io_offset = imx6ul_mmdc_io_offset,
		};

		/*
		* This structure is for passing necessary data for low level ocram
		* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
		@@ -290,7 +312,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
		val \|= BM_CLPCR_SBYOS;
		if (cpu_is_imx6sl())
		val \|= BM_CLPCR_BYPASS_PMIC_READY;
		if (cpu_is_imx6sl() \|\| cpu_is_imx6sx())
		if (cpu_is_imx6sl() \|\| cpu_is_imx6sx() \|\| cpu_is_imx6ul())
		val \|= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
		else
		val \|= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
		@@ -330,6 +352,10 @@ static int imx6q_suspend_finish(unsigned long val)
		* as we need to float DDR IO.
		*/
		local_flush_tlb_all();
		/* check if need to flush internal L2 cache */
		if (!((struct imx6_cpu_pm_info *)
		suspend_ocram_base)->l2_base.vbase)
		flush_cache_all();
		imx6_suspend_in_ocram_fn(suspend_ocram_base);
		}

		@@ -470,6 +496,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
		suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
		MX6Q_SUSPEND_OCRAM_SIZE, false);

		memset(suspend_ocram_base, 0, sizeof(*pm_info));
		pm_info = suspend_ocram_base;
		pm_info->pbase = ocram_pbase;
		pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
		@@ -505,12 +532,14 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
		goto gpc_map_failed;
		}

		ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
		if (socdata->pl310_compat) {
		ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
		if (ret) {
		pr_warn("%s: failed to get pl310-cache base %d!\n",
		__func__, ret);
		goto pl310_cache_map_failed;
		}
		}

		pm_info->ddr_type = imx_mmdc_get_ddr_type();
		pm_info->mmdc_io_num = socdata->mmdc_io_num;
		@@ -610,3 +639,8 @@ void __init imx6sx_pm_init(void)
		{
		imx6_pm_common_init(&imx6sx_pm_data);
		}

		void __init imx6ul_pm_init(void)
		{
		imx6_pm_common_init(&imx6ul_pm_data);
		}

arch/arm/mach-imx/suspend-imx6.S

+3 −0

Original line number	Diff line number	Diff line
		@@ -79,12 +79,15 @@
		/* sync L2 cache to drain L2's buffers to DRAM. */
		#ifdef CONFIG_CACHE_L2X0
		ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
		teq r11, #0
		beq 6f
		mov r6, #0x0
		str r6, [r11, #L2X0_CACHE_SYNC]
		1:
		ldr r6, [r11, #L2X0_CACHE_SYNC]
		ands r6, r6, #0x1
		bne 1b
		6:
		#endif

		.endm

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