Commit 00b24d44 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek into next/soc 

Do the initial setting of the pmic wrap interrupt before requesting the interrupt.
This fixes the corner-case where the pmic is initialized by the bootloader, but
not the pmic watchdog.

Add support for active wakeup to the scpsys. This allows to keep the power of
a scpsys domain  during suspend state.

With version v4.3 new subsystem clocks are added to the clock dirver. In late
init the kernel turns off all unused clocks. This can provoke a hang if
the kernel tries to access the venc and venc_lt power domain registers.
Add the necessary parent clocks for this power domains to
the scpsys so that no random hang happens.

The bootloader of mt6589, mt8135 and mt1827 does not turn on the arm-arch-timer.
As there is no opensource bootloader in the near future for this architectures
we enable the arch timer at kernel boot. We need the arch timer for SMP boot.

Add support for SMP on mt6589, mt8127 and mt8135.

* tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek

:
  ARM: mediatek: add smp bringup code
  ARM: mediatek: enable gpt6 on boot up to make arch timer working
  soc: mediatek: Fix random hang up issue while kernel init
  soc: mediatek: add scpsys support active_wakeup
  soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fc1f61f1 0cda0700

arch/arm/mach-mediatek/Makefile

+3 −0
Original line number Diff line number Diff line 
ifeq ($(CONFIG_SMP),y)

obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o

endif

obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o

arch/arm/mach-mediatek/mediatek.c

+27 −0
Original line number Diff line number Diff line
@@ -16,6 +16,32 @@ 
 */

#include <linux/init.h>

#include <asm/mach/arch.h>

#include <linux/of.h>

#include <linux/clk-provider.h>

#include <linux/clocksource.h>





#define GPT6_CON_MT65xx 0x10008060

#define GPT_ENABLE      0x31



static void __init mediatek_timer_init(void)

{

	void __iomem *gpt_base;



	if (of_machine_is_compatible("mediatek,mt6589") ||

	    of_machine_is_compatible("mediatek,mt8135") ||

	    of_machine_is_compatible("mediatek,mt8127")) {

		/* turn on GPT6 which ungates arch timer clocks */

		gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);



		/* enable clock and set to free-run */

		writel(GPT_ENABLE, gpt_base);

		iounmap(gpt_base);

	}



	of_clk_init(NULL);

	clocksource_of_init();

};



static const char * const mediatek_board_dt_compat[] = {

	"mediatek,mt6589",
@@ -27,4 +53,5 @@ static const char * const mediatek_board_dt_compat[] = { 


DT_MACHINE_START(MEDIATEK_DT, "Mediatek Cortex-A7 (Device Tree)")

	.dt_compat	= mediatek_board_dt_compat,

	.init_time	= mediatek_timer_init,

MACHINE_END

arch/arm/mach-mediatek/platsmp.c

0 → 100644
+141 −0
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-mediatek/platsmp.c

 *

 * Copyright (c) 2014 Mediatek Inc.

 * Author: Shunli Wang <shunli.wang@mediatek.com>

 *         Yingjoe Chen <yingjoe.chen@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */

#include <linux/io.h>

#include <linux/memblock.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/string.h>

#include <linux/threads.h>



#define MTK_MAX_CPU		8

#define MTK_SMP_REG_SIZE	0x1000



struct mtk_smp_boot_info {

	unsigned long smp_base;

	unsigned int jump_reg;

	unsigned int core_keys[MTK_MAX_CPU - 1];

	unsigned int core_regs[MTK_MAX_CPU - 1];

};



static const struct mtk_smp_boot_info mtk_mt8135_tz_boot = {

	0x80002000, 0x3fc,

	{ 0x534c4131, 0x4c415332, 0x41534c33 },

	{ 0x3f8, 0x3f8, 0x3f8 },

};



static const struct mtk_smp_boot_info mtk_mt6589_boot = {

	0x10002000, 0x34,

	{ 0x534c4131, 0x4c415332, 0x41534c33 },

	{ 0x38, 0x3c, 0x40 },

};



static const struct of_device_id mtk_tz_smp_boot_infos[] __initconst = {

	{ .compatible   = "mediatek,mt8135", .data = &mtk_mt8135_tz_boot },

	{ .compatible   = "mediatek,mt8127", .data = &mtk_mt8135_tz_boot },

};



static const struct of_device_id mtk_smp_boot_infos[] __initconst = {

	{ .compatible   = "mediatek,mt6589", .data = &mtk_mt6589_boot },

};



static void __iomem *mtk_smp_base;

static const struct mtk_smp_boot_info *mtk_smp_info;



static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)

{

	if (!mtk_smp_base)

		return -EINVAL;



	if (!mtk_smp_info->core_keys[cpu-1])

		return -EINVAL;



	writel_relaxed(mtk_smp_info->core_keys[cpu-1],

		mtk_smp_base + mtk_smp_info->core_regs[cpu-1]);



	arch_send_wakeup_ipi_mask(cpumask_of(cpu));



	return 0;

}



static void __init __mtk_smp_prepare_cpus(unsigned int max_cpus, int trustzone)

{

	int i, num;

	const struct of_device_id *infos;



	if (trustzone) {

		num = ARRAY_SIZE(mtk_tz_smp_boot_infos);

		infos = mtk_tz_smp_boot_infos;

	} else {

		num = ARRAY_SIZE(mtk_smp_boot_infos);

		infos = mtk_smp_boot_infos;

	}



	/* Find smp boot info for this SoC */

	for (i = 0; i < num; i++) {

		if (of_machine_is_compatible(infos[i].compatible)) {

			mtk_smp_info = infos[i].data;

			break;

		}

	}



	if (!mtk_smp_info) {

		pr_err("%s: Device is not supported\n", __func__);

		return;

	}



	if (trustzone) {

		/* smp_base(trustzone-bootinfo) is reserved by device tree */

		mtk_smp_base = phys_to_virt(mtk_smp_info->smp_base);

	} else {

		mtk_smp_base = ioremap(mtk_smp_info->smp_base, MTK_SMP_REG_SIZE);

		if (!mtk_smp_base) {

			pr_err("%s: Can't remap %lx\n", __func__,

				mtk_smp_info->smp_base);

			return;

		}

	}



	/*

	 * write the address of slave startup address into the system-wide

	 * jump register

	 */

	writel_relaxed(virt_to_phys(secondary_startup_arm),

			mtk_smp_base + mtk_smp_info->jump_reg);

}



static void __init mtk_tz_smp_prepare_cpus(unsigned int max_cpus)

{

	__mtk_smp_prepare_cpus(max_cpus, 1);

}



static void __init mtk_smp_prepare_cpus(unsigned int max_cpus)

{

	__mtk_smp_prepare_cpus(max_cpus, 0);

}



static struct smp_operations mt81xx_tz_smp_ops __initdata = {

	.smp_prepare_cpus = mtk_tz_smp_prepare_cpus,

	.smp_boot_secondary = mtk_boot_secondary,

};

CPU_METHOD_OF_DECLARE(mt81xx_tz_smp, "mediatek,mt81xx-tz-smp", &mt81xx_tz_smp_ops);



static struct smp_operations mt6589_smp_ops __initdata = {

	.smp_prepare_cpus = mtk_smp_prepare_cpus,

	.smp_boot_secondary = mtk_boot_secondary,

};

CPU_METHOD_OF_DECLARE(mt6589_smp, "mediatek,mt6589-smp", &mt6589_smp_ops);

drivers/soc/mediatek/mtk-pmic-wrap.c

+6 −4
Original line number Diff line number Diff line
@@ -725,10 +725,6 @@ static int pwrap_init(struct pmic_wrapper *wrp) 
	pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);

	pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);

	pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);

	pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);

	pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);

	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);

	pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);



	if (pwrap_is_mt8135(wrp)) {

		/* enable pwrap events and pwrap bridge in AP side */
@@ -896,6 +892,12 @@ static int pwrap_probe(struct platform_device *pdev) 
		return -ENODEV;

	}



	/* Initialize watchdog, may not be done by the bootloader */

	pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);

	pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);

	pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);

	pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);



	irq = platform_get_irq(pdev, 0);

	ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,

			"mt-pmic-pwrap", wrp);

drivers/soc/mediatek/mtk-scpsys.c

+60 −23
Original line number Diff line number Diff line
@@ -54,12 +54,16 @@ 
#define PWR_STATUS_USB			BIT(25)



enum clk_id {

	MT8173_CLK_NONE,

	MT8173_CLK_MM,

	MT8173_CLK_MFG,

	MT8173_CLK_NONE,

	MT8173_CLK_MAX = MT8173_CLK_NONE,

	MT8173_CLK_VENC,

	MT8173_CLK_VENC_LT,

	MT8173_CLK_MAX,

};



#define MAX_CLKS	2



struct scp_domain_data {

	const char *name;

	u32 sta_mask;
@@ -67,7 +71,8 @@ struct scp_domain_data { 
	u32 sram_pdn_bits;

	u32 sram_pdn_ack_bits;

	u32 bus_prot_mask;

	enum clk_id clk_id;

	enum clk_id clk_id[MAX_CLKS];

	bool active_wakeup;

};



static const struct scp_domain_data scp_domain_data[] __initconst = {
@@ -77,7 +82,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_VDE_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.clk_id = MT8173_CLK_MM,

		.clk_id = {MT8173_CLK_MM},

	},

	[MT8173_POWER_DOMAIN_VENC] = {

		.name = "venc",
@@ -85,7 +90,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_VEN_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.clk_id = MT8173_CLK_MM,

		.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},

	},

	[MT8173_POWER_DOMAIN_ISP] = {

		.name = "isp",
@@ -93,7 +98,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_ISP_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.clk_id = MT8173_CLK_MM,

		.clk_id = {MT8173_CLK_MM},

	},

	[MT8173_POWER_DOMAIN_MM] = {

		.name = "mm",
@@ -101,7 +106,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_DIS_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(12, 12),

		.clk_id = MT8173_CLK_MM,

		.clk_id = {MT8173_CLK_MM},

		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |

			MT8173_TOP_AXI_PROT_EN_MM_M1,

	},
@@ -111,7 +116,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_VEN2_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.clk_id = MT8173_CLK_MM,

		.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},

	},

	[MT8173_POWER_DOMAIN_AUDIO] = {

		.name = "audio",
@@ -119,7 +124,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_AUDIO_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.clk_id = MT8173_CLK_NONE,

		.clk_id = {MT8173_CLK_NONE},

	},

	[MT8173_POWER_DOMAIN_USB] = {

		.name = "usb",
@@ -127,7 +132,8 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_USB_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(15, 12),

		.clk_id = MT8173_CLK_NONE,

		.clk_id = {MT8173_CLK_NONE},

		.active_wakeup = true,

	},

	[MT8173_POWER_DOMAIN_MFG_ASYNC] = {

		.name = "mfg_async",
@@ -135,7 +141,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_MFG_ASYNC_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = 0,

		.clk_id = MT8173_CLK_MFG,

		.clk_id = {MT8173_CLK_MFG},

	},

	[MT8173_POWER_DOMAIN_MFG_2D] = {

		.name = "mfg_2d",
@@ -143,7 +149,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_MFG_2D_PWR_CON,

		.sram_pdn_bits = GENMASK(11, 8),

		.sram_pdn_ack_bits = GENMASK(13, 12),

		.clk_id = MT8173_CLK_NONE,

		.clk_id = {MT8173_CLK_NONE},

	},

	[MT8173_POWER_DOMAIN_MFG] = {

		.name = "mfg",
@@ -151,7 +157,7 @@ static const struct scp_domain_data scp_domain_data[] __initconst = { 
		.ctl_offs = SPM_MFG_PWR_CON,

		.sram_pdn_bits = GENMASK(13, 8),

		.sram_pdn_ack_bits = GENMASK(21, 16),

		.clk_id = MT8173_CLK_NONE,

		.clk_id = {MT8173_CLK_NONE},

		.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |

			MT8173_TOP_AXI_PROT_EN_MFG_M0 |

			MT8173_TOP_AXI_PROT_EN_MFG_M1 |
@@ -166,12 +172,13 @@ struct scp; 
struct scp_domain {

	struct generic_pm_domain genpd;

	struct scp *scp;

	struct clk *clk;

	struct clk *clk[MAX_CLKS];

	u32 sta_mask;

	void __iomem *ctl_addr;

	u32 sram_pdn_bits;

	u32 sram_pdn_ack_bits;

	u32 bus_prot_mask;

	bool active_wakeup;

};



struct scp {
@@ -212,12 +219,17 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) 
	u32 sram_pdn_ack = scpd->sram_pdn_ack_bits;

	u32 val;

	int ret;

	int i;



	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {

		ret = clk_prepare_enable(scpd->clk[i]);

		if (ret) {

			for (--i; i >= 0; i--)

				clk_disable_unprepare(scpd->clk[i]);



	if (scpd->clk) {

		ret = clk_prepare_enable(scpd->clk);

		if (ret)

			goto err_clk;

		}

	}



	val = readl(ctl_addr);

	val |= PWR_ON_BIT;
@@ -282,7 +294,10 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) 
	return 0;



err_pwr_ack:

	clk_disable_unprepare(scpd->clk);

	for (i = MAX_CLKS - 1; i >= 0; i--) {

		if (scpd->clk[i])

			clk_disable_unprepare(scpd->clk[i]);

	}

err_clk:

	dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
@@ -299,6 +314,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) 
	u32 pdn_ack = scpd->sram_pdn_ack_bits;

	u32 val;

	int ret;

	int i;



	if (scpd->bus_prot_mask) {

		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
@@ -360,8 +376,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) 
			expired = true;

	}



	if (scpd->clk)

		clk_disable_unprepare(scpd->clk);

	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)

		clk_disable_unprepare(scpd->clk[i]);



	return 0;
@@ -371,11 +387,22 @@ out: 
	return ret;

}



static bool scpsys_active_wakeup(struct device *dev)

{

	struct generic_pm_domain *genpd;

	struct scp_domain *scpd;



	genpd = pd_to_genpd(dev->pm_domain);

	scpd = container_of(genpd, struct scp_domain, genpd);



	return scpd->active_wakeup;

}



static int __init scpsys_probe(struct platform_device *pdev)

{

	struct genpd_onecell_data *pd_data;

	struct resource *res;

	int i, ret;

	int i, j, ret;

	struct scp *scp;

	struct clk *clk[MT8173_CLK_MAX];
@@ -405,6 +432,14 @@ static int __init scpsys_probe(struct platform_device *pdev) 
	if (IS_ERR(clk[MT8173_CLK_MFG]))

		return PTR_ERR(clk[MT8173_CLK_MFG]);



	clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");

	if (IS_ERR(clk[MT8173_CLK_VENC]))

		return PTR_ERR(clk[MT8173_CLK_VENC]);



	clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");

	if (IS_ERR(clk[MT8173_CLK_VENC_LT]))

		return PTR_ERR(clk[MT8173_CLK_VENC_LT]);



	scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,

			"infracfg");

	if (IS_ERR(scp->infracfg)) {
@@ -428,12 +463,14 @@ static int __init scpsys_probe(struct platform_device *pdev) 
		scpd->sram_pdn_bits = data->sram_pdn_bits;

		scpd->sram_pdn_ack_bits = data->sram_pdn_ack_bits;

		scpd->bus_prot_mask = data->bus_prot_mask;

		if (data->clk_id != MT8173_CLK_NONE)

			scpd->clk = clk[data->clk_id];

		scpd->active_wakeup = data->active_wakeup;

		for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)

			scpd->clk[j] = clk[data->clk_id[j]];



		genpd->name = data->name;

		genpd->power_off = scpsys_power_off;

		genpd->power_on = scpsys_power_on;

		genpd->dev_ops.active_wakeup = scpsys_active_wakeup;



		/*

		 * Initially turn on all domains to make the domains usable

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