Commit f6beb381 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Move engine-related mmio init to engines_init_mmio 



All the info we read in intel_device_info_init_mmio are engine-related
and since we already have an engine_init_mmio function we can just
perform the operations from there.

v2: clarify comment about forcewake requirements and pruning (Chris)

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-4-daniele.ceraolospurio@intel.com
parent 242613af

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+75 −1
Original line number Diff line number Diff line
@@ -450,6 +450,78 @@ void intel_engines_free(struct intel_gt *gt) 
	}

}



/*

 * Determine which engines are fused off in our particular hardware.

 * Note that we have a catch-22 situation where we need to be able to access

 * the blitter forcewake domain to read the engine fuses, but at the same time

 * we need to know which engines are available on the system to know which

 * forcewake domains are present. We solve this by intializing the forcewake

 * domains based on the full engine mask in the platform capabilities before

 * calling this function and pruning the domains for fused-off engines

 * afterwards.

 */

static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_device_info *info = mkwrite_device_info(i915);

	struct intel_uncore *uncore = gt->uncore;

	unsigned int logical_vdbox = 0;

	unsigned int i;

	u32 media_fuse;

	u16 vdbox_mask;

	u16 vebox_mask;



	if (INTEL_GEN(i915) < 11)

		return info->engine_mask;



	media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);



	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

		      GEN11_GT_VEBOX_DISABLE_SHIFT;



	for (i = 0; i < I915_MAX_VCS; i++) {

		if (!HAS_ENGINE(gt, _VCS(i))) {

			vdbox_mask &= ~BIT(i);

			continue;

		}



		if (!(BIT(i) & vdbox_mask)) {

			info->engine_mask &= ~BIT(_VCS(i));

			drm_dbg(&i915->drm, "vcs%u fused off\n", i);

			continue;

		}



		/*

		 * In Gen11, only even numbered logical VDBOXes are

		 * hooked up to an SFC (Scaler & Format Converter) unit.

		 * In TGL each VDBOX has access to an SFC.

		 */

		if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)

			RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i);

	}

	drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",

		vdbox_mask, VDBOX_MASK(gt));

	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));



	for (i = 0; i < I915_MAX_VECS; i++) {

		if (!HAS_ENGINE(gt, _VECS(i))) {

			vebox_mask &= ~BIT(i);

			continue;

		}



		if (!(BIT(i) & vebox_mask)) {

			info->engine_mask &= ~BIT(_VECS(i));

			drm_dbg(&i915->drm, "vecs%u fused off\n", i);

		}

	}

	drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",

		vebox_mask, VEBOX_MASK(gt));

	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));



	return info->engine_mask;

}



/**

 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers

 * @gt: pointer to struct intel_gt
@@ -460,7 +532,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) 
{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_device_info *device_info = mkwrite_device_info(i915);

	const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask;

	const unsigned int engine_mask = init_engine_mask(gt);

	unsigned int mask = 0;

	unsigned int i;

	int err;
@@ -497,6 +569,8 @@ int intel_engines_init_mmio(struct intel_gt *gt) 


	intel_setup_engine_capabilities(gt);



	intel_uncore_prune_engine_fw_domains(gt->uncore, gt);



	return 0;



cleanup:

drivers/gpu/drm/i915/i915_drv.c

+0 −4
Original line number Diff line number Diff line
@@ -531,10 +531,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 
	/* Try to make sure MCHBAR is enabled before poking at it */

	intel_setup_mchbar(dev_priv);



	intel_device_info_init_mmio(dev_priv);



	intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt);



	intel_uc_init_mmio(&dev_priv->gt.uc);



	ret = intel_engines_init_mmio(&dev_priv->gt);

drivers/gpu/drm/i915/intel_device_info.c

+0 −66
Original line number Diff line number Diff line
@@ -1089,69 +1089,3 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, 
		   yesno(caps->has_logical_contexts));

	drm_printf(p, "scheduler: %x\n", caps->scheduler);

}
 


/*

 * Determine which engines are fused off in our particular hardware. Since the

 * fuse register is in the blitter powerwell, we need forcewake to be ready at

 * this point (but later we need to prune the forcewake domains for engines that

 * are indeed fused off).

 */

void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)

{

	struct intel_device_info *info = mkwrite_device_info(dev_priv);

	struct intel_uncore *uncore = &dev_priv->uncore;

	struct intel_gt *gt = &dev_priv->gt;

	unsigned int logical_vdbox = 0;

	unsigned int i;

	u32 media_fuse;

	u16 vdbox_mask;

	u16 vebox_mask;



	if (INTEL_GEN(dev_priv) < 11)

		return;



	media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);



	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

		      GEN11_GT_VEBOX_DISABLE_SHIFT;



	for (i = 0; i < I915_MAX_VCS; i++) {

		if (!HAS_ENGINE(gt, _VCS(i))) {

			vdbox_mask &= ~BIT(i);

			continue;

		}



		if (!(BIT(i) & vdbox_mask)) {

			info->engine_mask &= ~BIT(_VCS(i));

			drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i);

			continue;

		}



		/*

		 * In Gen11, only even numbered logical VDBOXes are

		 * hooked up to an SFC (Scaler & Format Converter) unit.

		 * In TGL each VDBOX has access to an SFC.

		 */

		if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0)

			RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i);

	}

	drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n",

		vdbox_mask, VDBOX_MASK(gt));

	GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));



	for (i = 0; i < I915_MAX_VECS; i++) {

		if (!HAS_ENGINE(gt, _VECS(i))) {

			vebox_mask &= ~BIT(i);

			continue;

		}



		if (!(BIT(i) & vebox_mask)) {

			info->engine_mask &= ~BIT(_VECS(i));

			drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i);

		}

	}

	drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n",

		vebox_mask, VEBOX_MASK(gt));

	GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));

}

drivers/gpu/drm/i915/intel_device_info.h

+0 −2
Original line number Diff line number Diff line
@@ -250,8 +250,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info, 
void intel_device_info_print_topology(const struct sseu_dev_info *sseu,

				      struct drm_printer *p);



void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);



void intel_driver_caps_print(const struct intel_driver_caps *caps,

			     struct drm_printer *p);

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