Commit 242613af authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: Use the gt in HAS_ENGINE 



A follow up patch will move the engine mask under the gt structure,
so get ready for that.

v2: switch the remaining gvt case using dev_priv->gt to gvt->gt (Chris)

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> #v1
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-3-daniele.ceraolospurio@intel.com
parent fdeb6d02

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) 
		return -ENODEV;



	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {

		if (!HAS_ENGINE(i915, i))

		if (!HAS_ENGINE(gt, i))

			continue;



		err = intel_engine_setup(gt, i);

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt) 
		 * RPS interrupts will get enabled/disabled on demand when RPS

		 * itself is enabled/disabled.

		 */

		if (HAS_ENGINE(gt->i915, VECS0)) {

		if (HAS_ENGINE(gt, VECS0)) {

			pm_irqs |= PM_VEBOX_USER_INTERRUPT;

			gt->pm_ier |= PM_VEBOX_USER_INTERRUPT;

		}

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

+4 −3
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ struct __guc_ads_blob { 


static void __guc_ads_init(struct intel_guc *guc)

{

	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;

	struct intel_gt *gt = guc_to_gt(guc);

	struct drm_i915_private *dev_priv = gt->i915;

	struct __guc_ads_blob *blob = guc->ads_blob;

	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;

	u32 base;
@@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc) 
	blob->system_info.rcs_enabled = 1;

	blob->system_info.bcs_enabled = 1;



	blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);

	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);

	blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt);

	blob->system_info.vebox_enable_mask = VEBOX_MASK(gt);

	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;



	base = intel_guc_ggtt_offset(guc, guc->ads_vma);

drivers/gpu/drm/i915/gvt/handlers.c

+1 −1
Original line number Diff line number Diff line
@@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 
	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \

	if (HAS_ENGINE(dev_priv, VCS1)) \

	if (HAS_ENGINE(gvt->gt, VCS1)) \

		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \

} while (0)

drivers/gpu/drm/i915/gvt/interrupt.c

+1 −1
Original line number Diff line number Diff line
@@ -540,7 +540,7 @@ static void gen8_init_irq( 
	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);

	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);



	if (HAS_ENGINE(gvt->gt->i915, VCS1)) {

	if (HAS_ENGINE(gvt->gt, VCS1)) {

		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,

			INTEL_GVT_IRQ_INFO_GT1);

		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,

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