Commit f6aee505 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-timers-2020-06-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 timer updates from Thomas Gleixner:
 "X86 timer specific updates:

   - Add TPAUSE based delay which allows the CPU to enter an optimized
     power state while waiting for the delay to pass. The delay is based
     on TSC cycles.

   - Add tsc_early_khz command line parameter to workaround the problem
     that overclocked CPUs can report the wrong frequency via CPUID.16h
     which causes the refined calibration to fail because the delta to
     the initial frequency value is too big. With the parameter users
     can provide an halfways accurate initial value"

* tag 'x86-timers-2020-06-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/tsc: Add tsc_early_khz command line parameter
  x86/delay: Introduce TPAUSE delay
  x86/delay: Refactor delay_mwaitx() for TPAUSE support
  x86/delay: Preparatory code cleanup
parents dabc4df2 bd35c77e

Documentation/admin-guide/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -5093,6 +5093,12 @@ 
			interruptions from clocksource watchdog are not

			acceptable).



	tsc_early_khz=  [X86] Skip early TSC calibration and use the given

			value instead. Useful when the early TSC frequency discovery

			procedure is not reliable, such as on overclocked systems

			with CPUID.16h support and partial CPUID.15h support.

			Format: <unsigned int>



	tsx=		[X86] Control Transactional Synchronization

			Extensions (TSX) feature in Intel processors that

			support TSX control.

arch/x86/Kconfig.assembler

+4 −0
Original line number Diff line number Diff line
@@ -15,3 +15,7 @@ config AS_SHA256_NI 
	def_bool $(as-instr,sha256msg1 %xmm0$(comma)%xmm1)

	help

	  Supported by binutils >= 2.24 and LLVM integrated assembler

config AS_TPAUSE

	def_bool $(as-instr,tpause %ecx)

	help

	  Supported by binutils >= 2.31.1 and LLVM integrated assembler >= V7

arch/x86/include/asm/delay.h

+3 −1
Original line number Diff line number Diff line
@@ -3,8 +3,10 @@ 
#define _ASM_X86_DELAY_H



#include <asm-generic/delay.h>

#include <linux/init.h>



void use_tsc_delay(void);

void __init use_tsc_delay(void);

void __init use_tpause_delay(void);

void use_mwaitx_delay(void);



#endif /* _ASM_X86_DELAY_H */

arch/x86/include/asm/mwait.h

+23 −1
Original line number Diff line number Diff line
@@ -20,8 +20,10 @@ 


#define MWAIT_ECX_INTERRUPT_BREAK	0x1

#define MWAITX_ECX_TIMER_ENABLE		BIT(1)

#define MWAITX_MAX_LOOPS		((u32)-1)

#define MWAITX_MAX_WAIT_CYCLES		UINT_MAX

#define MWAITX_DISABLE_CSTATES		0xf0

#define TPAUSE_C01_STATE		1

#define TPAUSE_C02_STATE		0



u32 get_umwait_control_msr(void);
@@ -122,4 +124,24 @@ static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) 
	current_clr_polling();

}



/*

 * Caller can specify whether to enter C0.1 (low latency, less

 * power saving) or C0.2 state (saves more power, but longer wakeup

 * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR

 * which can force requests for C0.2 to be downgraded to C0.1.

 */

static inline void __tpause(u32 ecx, u32 edx, u32 eax)

{

	/* "tpause %ecx, %edx, %eax;" */

	#ifdef CONFIG_AS_TPAUSE

	asm volatile("tpause %%ecx\n"

		     :

		     : "c"(ecx), "d"(edx), "a"(eax));

	#else

	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n"

		     :

		     : "c"(ecx), "d"(edx), "a"(eax));

	#endif

}



#endif /* _ASM_X86_MWAIT_H */

arch/x86/kernel/time.c

+3 −0
Original line number Diff line number Diff line
@@ -103,6 +103,9 @@ static __init void x86_late_time_init(void) 
	 */

	x86_init.irqs.intr_mode_init();

	tsc_init();



	if (static_cpu_has(X86_FEATURE_WAITPKG))

		use_tpause_delay();

}



/*

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