Commit f5236225 authored by Dan Williams's avatar Dan Williams Committed by Russell King
Browse files

[ARM] 3967/1: xsc3: make branch predication configurable on xsc3 



Remove BTB_ENABLE from proc-xsc3.S

On some early revisions of xsc3 enabling the branch target buffer can cause
crashes, see erratum #42.

Cc: Lennert Buytenhek <buytenh@wantstofly.org>

Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 0e5fdca7

arch/arm/mm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -580,7 +580,7 @@ config CPU_CACHE_ROUND_ROBIN 


config CPU_BPREDICT_DISABLE

	bool "Disable branch prediction"

	depends on CPU_ARM1020 || CPU_V6

	depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3

	help

	  Say Y here to disable branch prediction.  If unsure, say N.

arch/arm/mm/proc-xsc3.S

+0 −7
Original line number Diff line number Diff line
@@ -56,11 +56,6 @@ 
 */

#define L2_CACHE_ENABLE	1



/*

 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)

 */

#define BTB_ENABLE	0



/*

 * This macro is used to wait for a CP15 write and is needed

 * when we have to ensure that the last operation to the co-pro
@@ -434,9 +429,7 @@ __xsc3_setup: 
	mrc	p15, 0, r0, c1, c0, 0		@ get control register

	bic	r0, r0, r5			@ .... .... .... ..A.

	orr	r0, r0, r6			@ .... .... .... .C.M

#if BTB_ENABLE

	orr	r0, r0, #0x00000800		@ ..VI Z..S .... ....

#endif

#if L2_CACHE_ENABLE

	orr 	r0, r0, #0x04000000		@ L2 enable

#endif

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