Commit f3824deb authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a77980: Add RCLK for watchdog timer 



On R-Car V3H, RCLK can be switched between EXTALR and the On-Chip
Oscillator using mode pin MD19.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent cd51e427

drivers/clk/renesas/r8a77980-cpg-mssr.c

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ enum clk_ids { 
	CLK_S2,

	CLK_S3,

	CLK_SDSRC,

	CLK_OCO,



	/* Module Clocks */

	MOD_CLK_BASE
@@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { 
	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",	CLK_SDSRC,	   CLK_PLL1_DIV2,  2, 1),

	DEF_RATE(".oco",	CLK_OCO,           32768),



	/* Core Clock Outputs */

	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
@@ -98,6 +100,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { 
	DEF_DIV6P1("mso",	R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),



	DEF_GEN3_OSC("osc",	R8A77980_CLK_OSC,   CLK_EXTAL,     8),

	DEF_GEN3_MDSEL("r",	R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),

};



static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
@@ -119,6 +122,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { 
	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),

	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),

	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S2D2),

	DEF_MOD("rwdt",			 402,	R8A77980_CLK_R),

	DEF_MOD("intc-ex",		 407,	R8A77980_CLK_CP),

	DEF_MOD("intc-ap",		 408,	R8A77980_CLK_S0D3),

	DEF_MOD("hscif3",		 517,	R8A77980_CLK_S3D1),

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