clk: renesas: rcar-gen3: Add support for mode pin clock selection (cd51e427) · Commits · 戴 / test

drivers/clk/renesas/rcar-gen3-cpg.c

+4 −6

Original line number	Diff line number	Diff line
		@@ -539,16 +539,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
		parent = clks[cpg_clk_extalr];
		break;

		case CLK_TYPE_GEN3_PE:
		case CLK_TYPE_GEN3_MDSEL:
		/*
		* Peripheral clock with a fixed divider, selectable between
		* clean and spread spectrum parents using MD12
		* Clock selectable between two parents and two fixed dividers
		* using a mode pin
		*/
		if (cpg_mode & BIT(12)) {
		/* Clean */
		if (cpg_mode & BIT(core->offset)) {
		div = core->div & 0xffff;
		} else {
		/* SCCG */
		parent = clks[core->parent >> 16];
		if (IS_ERR(parent))
		return ERR_CAST(parent);

+9 −4

Original line number	Diff line number	Diff line
		@@ -20,7 +20,7 @@ enum rcar_gen3_clk_types {
		CLK_TYPE_GEN3_PLL4,
		CLK_TYPE_GEN3_SD,
		CLK_TYPE_GEN3_R,
		CLK_TYPE_GEN3_PE,
		CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
		CLK_TYPE_GEN3_Z,
		CLK_TYPE_GEN3_Z2,
		CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
		@@ -30,11 +30,16 @@ enum rcar_gen3_clk_types {
		#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
		DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)

		#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
		DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
		(_parent0) << 16 \| (_parent1), \
		.div = (_div0) << 16 \| (_div1), .offset = _md)

		#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
		_div_clean) \
		DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
		(_parent_sscg) << 16 \| (_parent_clean), \
		.div = (_div_sscg) << 16 \| (_div_clean))
		DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
		_parent_clean, _div_clean)

		#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
		DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)