Commit f349f772 authored by Bernard Zhao's avatar Bernard Zhao Committed by Alex Deucher
Browse files

drm/amd: fix typoes in comments 



Change the comment typo: "programm" -> "program".

Signed-off-by: default avatarBernard Zhao <bernard@vivo.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 027f2d27

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ struct amdgpu_bo_list_entry; 
#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)

#define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)



/* How to programm VM fault handling */

/* How to program VM fault handling */

#define AMDGPU_VM_FAULT_STOP_NEVER	0

#define AMDGPU_VM_FAULT_STOP_FIRST	1

#define AMDGPU_VM_FAULT_STOP_ALWAYS	2

drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c

+2 −2
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev) 
	/* Set the write pointer delay */

	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);



	/* programm the 4GB memory segment for rptr and ring buffer */

	/* program the 4GB memory segment for rptr and ring buffer */

	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

				   (0x7 << 16) | (0x1 << 31));
@@ -541,7 +541,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 
	uint64_t addr;

	uint32_t size;



	/* programm the VCPU memory controller bits 0-27 */

	/* program the VCPU memory controller bits 0-27 */

	addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;

	size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;

	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

+2 −2
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 
	uint64_t offset;

	uint32_t size;



	/* programm memory controller bits 0-27 */

	/* program memory controller bits 0-27 */

	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

			lower_32_bits(adev->uvd.inst->gpu_addr));

	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -404,7 +404,7 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) 
	/* set the wb address */

	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));



	/* programm the RB_BASE for ring buffer */

	/* program the RB_BASE for ring buffer */

	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

			lower_32_bits(ring->gpu_addr));

	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+2 −2
Original line number Diff line number Diff line
@@ -583,7 +583,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 
	uint64_t offset;

	uint32_t size;



	/* programm memory controller bits 0-27 */

	/* program memory controller bits 0-27 */

	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

			lower_32_bits(adev->uvd.inst->gpu_addr));

	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
@@ -825,7 +825,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) 
	/* set the wb address */

	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));



	/* programm the RB_BASE for ring buffer */

	/* program the RB_BASE for ring buffer */

	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

			lower_32_bits(ring->gpu_addr));

	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1073,7 +1073,7 @@ static int uvd_v7_0_start(struct amdgpu_device *adev) 
		WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,

				(upper_32_bits(ring->gpu_addr) >> 2));



		/* programm the RB_BASE for ring buffer */

		/* program the RB_BASE for ring buffer */

		WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

				lower_32_bits(ring->gpu_addr));

		WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

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