Commit 027f2d27 authored by Bernard Zhao's avatar Bernard Zhao Committed by Alex Deucher
Browse files

drm/radeon: fix typoes in comments 



Change the comment typo: "programm" -> "program".

Signed-off-by: default avatarBernard Zhao <bernard@vivo.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52ef3a1a

drivers/gpu/drm/radeon/uvd_v1_0.c

+2 −2
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ int uvd_v1_0_resume(struct radeon_device *rdev) 
	if (r)

		return r;



	/* programm the VCPU memory controller bits 0-27 */

	/* program the VCPU memory controller bits 0-27 */

	addr = (rdev->uvd.gpu_addr >> 3) + 16;

	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;

	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
@@ -360,7 +360,7 @@ int uvd_v1_0_start(struct radeon_device *rdev) 
	/* Set the write pointer delay */

	WREG32(UVD_RBC_RB_WPTR_CNTL, 0);



	/* programm the 4GB memory segment for rptr and ring buffer */

	/* program the 4GB memory segment for rptr and ring buffer */

	WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

				   (0x7 << 16) | (0x1 << 31));

drivers/gpu/drm/radeon/uvd_v2_2.c

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ int uvd_v2_2_resume(struct radeon_device *rdev) 
	if (r)

		return r;



	/* programm the VCPU memory controller bits 0-27 */

	/* program the VCPU memory controller bits 0-27 */

	addr = rdev->uvd.gpu_addr >> 3;

	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;

	WREG32(UVD_VCPU_CACHE_OFFSET0, addr);

drivers/gpu/drm/radeon/uvd_v4_2.c

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ int uvd_v4_2_resume(struct radeon_device *rdev) 
	uint64_t addr;

	uint32_t size;



	/* programm the VCPU memory controller bits 0-27 */

	/* program the VCPU memory controller bits 0-27 */



	/* skip over the header of the new firmware format */

	if (rdev->uvd.fw_header_present)

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