Merge branch 'hns3-next' (f3184645) · Commits · 戴 / test

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -50,7 +50,8 @@ static const struct pci_device_id hns3_pci_tbl[] = {
		{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
		HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
		{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
		{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
		{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
		HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
		/* required last entry */
		{0, }
		};

+2 −0

Original line number	Diff line number	Diff line
		@@ -358,6 +358,8 @@ struct hclge_pf_res_cmd {
		__le16 buf_size;
		__le16 msixcap_localid_ba_nic;
		__le16 msixcap_localid_ba_rocee;
		#define HCLGE_MSIX_OFT_ROCEE_S 0
		#define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
		#define HCLGE_PF_VEC_NUM_S 0
		#define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
		__le16 pf_intr_vector_number;

+6 −2

Original line number	Diff line number	Diff line
		@@ -932,6 +932,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
		hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;

		if (hnae3_dev_roce_supported(hdev)) {
		hdev->roce_base_msix_offset =
		hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
		HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
		hdev->num_roce_msi =
		hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
		HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
		@@ -939,7 +942,8 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
		/* PF should have NIC vectors and Roce vectors,
		* NIC vectors are queued before Roce vectors.
		*/
		hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
		hdev->num_msi = hdev->num_roce_msi +
		hdev->roce_base_msix_offset;
		} else {
		hdev->num_msi =
		hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
		@@ -2037,7 +2041,7 @@ static int hclge_init_msi(struct hclge_dev *hdev)
		hdev->num_msi_left = vectors;
		hdev->base_msi_vector = pdev->irq;
		hdev->roce_base_vector = hdev->base_msi_vector +
		HCLGE_ROCE_VECTOR_OFFSET;
		hdev->roce_base_msix_offset;

		hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
		sizeof(u16), GFP_KERNEL);

+1 −2

Original line number	Diff line number	Diff line
		@@ -16,8 +16,6 @@

		#define HCLGE_INVALID_VPORT 0xffff

		#define HCLGE_ROCE_VECTOR_OFFSET 96

		#define HCLGE_PF_CFG_BLOCK_SIZE 32
		#define HCLGE_PF_CFG_DESC_NUM \
		(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
		@@ -509,6 +507,7 @@ struct hclge_dev {
		u16 num_msi;
		u16 num_msi_left;
		u16 num_msi_used;
		u16 roce_base_msix_offset;
		u32 base_msi_vector;
		u16 *vector_status;
		int *vector_irq;

+14 −0

Original line number	Diff line number	Diff line
		@@ -82,6 +82,7 @@ struct hclgevf_cmq {
		enum hclgevf_opcode_type {
		/* Generic command */
		HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
		HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
		/* TQP command */
		HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
		HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
		@@ -134,6 +135,19 @@ struct hclgevf_query_version_cmd {
		__le32 firmware_rsv[5];
		};

		#define HCLGEVF_MSIX_OFT_ROCEE_S 0
		#define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
		#define HCLGEVF_VEC_NUM_S 0
		#define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
		struct hclgevf_query_res_cmd {
		__le16 tqp_num;
		__le16 reserved;
		__le16 msixcap_localid_ba_nic;
		__le16 msixcap_localid_ba_rocee;
		__le16 vf_intr_vector_number;
		__le16 rsv[7];
		};

		#define HCLGEVF_RSS_HASH_KEY_OFFSET 4
		#define HCLGEVF_RSS_HASH_KEY_NUM 16
		struct hclgevf_rss_config_cmd {