Commit 375dd5e4 authored by Jian Shen's avatar Jian Shen Committed by David S. Miller
Browse files

net: hns3: Refine the MSIX allocation for PF 



The offset of msix number for roce is different between different
revision id. We should get it from firmware, instead of a fix value.
This patch refines the msix allocation, make it compatible.

Signed-off-by: default avatarJian Shen <shenjian15@huawei.com>
Signed-off-by: default avatarPeng Li <lipeng321@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 07acf909

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+2 −0
Original line number Diff line number Diff line
@@ -358,6 +358,8 @@ struct hclge_pf_res_cmd { 
	__le16 buf_size;

	__le16 msixcap_localid_ba_nic;

	__le16 msixcap_localid_ba_rocee;

#define HCLGE_MSIX_OFT_ROCEE_S		0

#define HCLGE_MSIX_OFT_ROCEE_M		GENMASK(15, 0)

#define HCLGE_PF_VEC_NUM_S		0

#define HCLGE_PF_VEC_NUM_M		GENMASK(7, 0)

	__le16 pf_intr_vector_number;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+6 −2
Original line number Diff line number Diff line
@@ -932,6 +932,9 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) 
	hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;



	if (hnae3_dev_roce_supported(hdev)) {

		hdev->roce_base_msix_offset =

		hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),

				HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);

		hdev->num_roce_msi =

		hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),

				HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
@@ -939,7 +942,8 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev) 
		/* PF should have NIC vectors and Roce vectors,

		 * NIC vectors are queued before Roce vectors.

		 */

		hdev->num_msi = hdev->num_roce_msi  + HCLGE_ROCE_VECTOR_OFFSET;

		hdev->num_msi = hdev->num_roce_msi  +

				hdev->roce_base_msix_offset;

	} else {

		hdev->num_msi =

		hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
@@ -2037,7 +2041,7 @@ static int hclge_init_msi(struct hclge_dev *hdev) 
	hdev->num_msi_left = vectors;

	hdev->base_msi_vector = pdev->irq;

	hdev->roce_base_vector = hdev->base_msi_vector +

				HCLGE_ROCE_VECTOR_OFFSET;

				hdev->roce_base_msix_offset;



	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,

					   sizeof(u16), GFP_KERNEL);

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+1 −2
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@ 


#define HCLGE_INVALID_VPORT 0xffff



#define HCLGE_ROCE_VECTOR_OFFSET	96



#define HCLGE_PF_CFG_BLOCK_SIZE		32

#define HCLGE_PF_CFG_DESC_NUM \

	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
@@ -509,6 +507,7 @@ struct hclge_dev { 
	u16 num_msi;

	u16 num_msi_left;

	u16 num_msi_used;

	u16 roce_base_msix_offset;

	u32 base_msi_vector;

	u16 *vector_status;

	int *vector_irq;

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