Commit f02ac414 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" 



This reverts commit 62037fff.

L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-1-mika.kuoppala@linux.intel.com
parent 24fe5f2a

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+0 −1
Original line number Diff line number Diff line
@@ -236,7 +236,6 @@ 
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */

#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE		REG_BIT(10) /* gen12 */

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH		REG_BIT(9)  /* gen12 */

#define   PIPE_CONTROL_NOTIFY				(1<<8)

drivers/gpu/drm/i915/gt/intel_lrc.c

+0 −1
Original line number Diff line number Diff line
@@ -4579,7 +4579,6 @@ static int gen12_emit_flush_render(struct i915_request *request, 
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;



		flags |= PIPE_CONTROL_STORE_DATA_INDEX;

		flags |= PIPE_CONTROL_QW_WRITE;

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