Commit 62037fff authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/tgl: Include ro parts of l3 to invalidate 



Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-2-mika.kuoppala@linux.intel.com
parent 613716bb

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+1 −0
Original line number Diff line number Diff line
@@ -233,6 +233,7 @@ 
#define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH	(1<<12) /* gen6+ */

#define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE	(1<<11) /* MBZ on ILK */

#define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE		(1<<10) /* GM45+ only */

#define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE		REG_BIT(10) /* gen12 */

#define   PIPE_CONTROL_INDIRECT_STATE_DISABLE		(1<<9)

#define   PIPE_CONTROL_NOTIFY				(1<<8)

#define   PIPE_CONTROL_FLUSH_ENABLE			(1<<7) /* gen7+ */

drivers/gpu/drm/i915/gt/intel_lrc.c

+1 −0
Original line number Diff line number Diff line
@@ -3230,6 +3230,7 @@ static int gen12_emit_flush_render(struct i915_request *request, 
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;

		flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;



		flags |= PIPE_CONTROL_STORE_DATA_INDEX;

		flags |= PIPE_CONTROL_QW_WRITE;

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