Commit efb1e0b0 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie',... 

Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next

* clk-ingenic:
  clk: ingenic: Remove set but not used variable 'enable'
  clk: ingenic: Fix doc of ingenic_cgu_div_info
  clk: ingenic: Fix round_rate misbehaving with non-integer dividers
  clk: ingenic: jz4740: Fix gating of UDC clock

* clk-mtk-mux:
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2

* clk-qcom-sdm845-pcie:
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

* clk-mtk-crit:
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro

* clk-mtk:
  clk: mediatek: correct cpu clock name for MT8173 SoC
parents 75f486c0 635bd69b d3174bc8 4b5a59a2 b35656de 64f4466c

drivers/clk/ingenic/cgu.c

+6 −7
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	const struct ingenic_cgu_clk_info *clk_info;

	const struct ingenic_cgu_pll_info *pll_info;

	unsigned m, n, od_enc, od;

	bool bypass, enable;

	bool bypass;

	unsigned long flags;

	u32 ctl;
@@ -103,7 +103,6 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	od_enc &= GENMASK(pll_info->od_bits - 1, 0);

	bypass = !pll_info->no_bypass_bit &&

		 !!(ctl & BIT(pll_info->bypass_bit));

	enable = !!(ctl & BIT(pll_info->enable_bit));



	if (bypass)

		return parent_rate;
@@ -426,16 +425,16 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, 
	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	long rate = *parent_rate;

	unsigned int div = 1;



	clk_info = &cgu->clock_info[ingenic_clk->idx];



	if (clk_info->type & CGU_CLK_DIV)

		rate /= ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);

		div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);

	else if (clk_info->type & CGU_CLK_FIXDIV)

		rate /= clk_info->fixdiv.div;

		div = clk_info->fixdiv.div;



	return rate;

	return DIV_ROUND_UP(*parent_rate, div);

}



static int
@@ -455,7 +454,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, 


	if (clk_info->type & CGU_CLK_DIV) {

		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);

		rate = parent_rate / div;

		rate = DIV_ROUND_UP(parent_rate, div);



		if (rate != req_rate)

			return -EINVAL;

drivers/clk/ingenic/cgu.h

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ struct ingenic_cgu_mux_info { 
 * @reg: offset of the divider control register within the CGU

 * @shift: number of bits to left shift the divide value by (ie. the index of

 *         the lowest bit of the divide value within its control register)

 * @div: number of bits to divide the divider value by (i.e. if the

 * @div: number to divide the divider value by (i.e. if the

 *	 effective divider value is the value written to the register

 *	 multiplied by some constant)

 * @bits: the size of the divide value in bits

drivers/clk/ingenic/jz4740-cgu.c

+1 −1
Original line number Diff line number Diff line
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 
		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },

		.mux = { CGU_REG_CPCCR, 29, 1 },

		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },

		.gate = { CGU_REG_SCR, 6 },

		.gate = { CGU_REG_SCR, 6, true },

	},



	/* Gate-only clocks */

drivers/clk/mediatek/clk-gate.c

+3 −1
Original line number Diff line number Diff line
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate( 
		int clr_ofs,

		int sta_ofs,

		u8 bit,

		const struct clk_ops *ops)

		const struct clk_ops *ops,

		unsigned long flags)

{

	struct mtk_clk_gate *cg;

	struct clk *clk;
@@ -172,6 +173,7 @@ struct clk *mtk_clk_register_gate( 
	init.parent_names = parent_name ? &parent_name : NULL;

	init.num_parents = parent_name ? 1 : 0;

	init.ops = ops;

	init.flags = flags;



	cg->regmap = regmap;

	cg->set_ofs = set_ofs;

drivers/clk/mediatek/clk-gate.h

+2 −1
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate( 
		int clr_ofs,

		int sta_ofs,

		u8 bit,

		const struct clk_ops *ops);

		const struct clk_ops *ops,

		unsigned long flags);



#endif /* __DRV_CLK_GATE_H */

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