clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks (4b5a59a2) · Commits · 戴 / test

The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the PHY, describe this relationship. Signed-off-by:

drivers/clk/qcom/gcc-sdm845.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -1697,6 +1697,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
		.enable_mask = BIT(4),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_pipe_clk",
		.parent_names = (const char *[]){ "pcie_0_pipe_clk" },
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1796,6 +1799,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
		.enable_mask = BIT(30),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_1_pipe_clk",
		.parent_names = (const char *[]){ "pcie_1_pipe_clk" },
		.num_parents = 1,
		.ops = &clk_branch2_ops,
		},
		},