Commit ef3c139b authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'ti-k3-dt-for-v5.10-part2' of... 

Merge tag 'ti-k3-dt-for-v5.10-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt

Second and final device tree updates towards 5.10-rc1 for TI K3 platform.

* tag 'ti-k3-dt-for-v5.10-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (23 commits)
  arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
  arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
  arm64: dts: ti: k3-j7200-main: Add USB controller
  arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
  arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
  dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
  arm64: dts: ti: k3-j721e-common-proc-board: align GPIO hog names with dtschema
  arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
  arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes
  arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash node
  arm64: dts: ti: k3-j7200-mcu-wakeup: Add HyperBus node
  arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
  arm64: dts: ti: k3-j7200: Add I2C nodes
  arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs
  arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node
  arm64: dts: ti: k3-j7200-main: add main navss cpts node
  arm64: dts: ti: k3-j7200: add DMA support
  arm64: dts: ti: Add support for J7200 Common Processor Board
  arm64: dts: ti: Add support for J7200 SoC
  dt-bindings: arm: ti: Add bindings for J7200 SoC
  ...

Link: https://lore.kernel.org/r/20201002134559.orvmgbns57qlyn3i@akan


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7d0c5aee bbcb0522

Documentation/devicetree/bindings/arm/ti/k3.txt

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Texas Instruments K3 Multicore SoC architecture device tree bindings

--------------------------------------------------------------------



Platforms based on Texas Instruments K3 Multicore SoC architecture

shall follow the following scheme:



SoCs

----



Each device tree root node must specify which exact SoC in K3 Multicore SoC

architecture it uses, using one of the following compatible values:



- AM654

  compatible = "ti,am654";



- J721E

  compatible = "ti,j721e";



Boards

------



In addition, each device tree root node must specify which one or more

of the following board-specific compatible values:



- AM654 EVM

  compatible = "ti,am654-evm", "ti,am654";

Documentation/devicetree/bindings/arm/ti/k3.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/ti/k3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Texas Instruments K3 Multicore SoC architecture device tree bindings



maintainers:

  - Nishanth Menon <nm@ti.com>



description: |

  Platforms based on Texas Instruments K3 Multicore SoC architecture

  shall have the following properties.



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:



      - description: K3 AM654 SoC

        items:

          - enum:

              - ti,am654-evm

          - const: ti,am654



      - description: K3 J721E SoC

        items:

          - const: ti,j721e



      - description: K3 J7200 SoC

        items:

          - const: ti,j7200

...

MAINTAINERS

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@@ -2637,7 +2637,7 @@ M: Tero Kristo <t-kristo@ti.com> 
M:	Nishanth Menon <nm@ti.com>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Supported

F:	Documentation/devicetree/bindings/arm/ti/k3.txt

F:	Documentation/devicetree/bindings/arm/ti/k3.yaml

F:	arch/arm64/boot/dts/ti/Makefile

F:	arch/arm64/boot/dts/ti/k3-*

F:	include/dt-bindings/pinctrl/k3.h

arch/arm64/boot/dts/ti/Makefile

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@@ -3,9 +3,11 @@ 
# Make file to build device tree binaries for boards based on

# Texas Instruments Inc processors

#

# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

# Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/

#



dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb

dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb



dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
 
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb



dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

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// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/

 */



/dts-v1/;



#include "k3-j7200-som-p0.dtsi"

#include <dt-bindings/net/ti-dp83867.h>

#include <dt-bindings/mux/ti-serdes.h>



/ {

	chosen {

		stdout-path = "serial2:115200n8";

		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";

	};

};



&wkup_pmx0 {

	mcu_cpsw_pins_default: mcu-cpsw-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */

			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */

			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */

			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */

			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */

			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */

			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */

			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */

			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */

			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */

			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */

			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */

		>;

	};



	mcu_mdio_pins_default: mcu-mdio1-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */

			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */

		>;

	};

};



&main_pmx0 {

	main_i2c0_pins_default: main-i2c0-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */

			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */

		>;

	};



	main_i2c1_pins_default: main-i2c1-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */

			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */

		>;

	};



	main_mmc1_pins_default: main-mmc1-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */

			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */

			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */

			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */

			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */

			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */

			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */

			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */

		>;

	};



	main_usbss0_pins_default: main-usbss0-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */

		>;

	};

};



&wkup_uart0 {

	/* Wakeup UART is used by System firmware */

	status = "disabled";

};



&main_uart0 {

	/* Shared with ATF on this platform */

	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;

};



&main_uart2 {

	/* MAIN UART 2 is used by R5F firmware */

	status = "disabled";

};



&main_uart3 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart4 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart5 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart6 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart7 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart8 {

	/* UART not brought out */

	status = "disabled";

};



&main_uart9 {

	/* UART not brought out */

	status = "disabled";

};



&mcu_cpsw {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

};



&davinci_mdio {

	phy0: ethernet-phy@0 {

		reg = <0>;

		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

	};

};



&cpsw_port1 {

	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};



&main_i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_i2c0_pins_default>;

	clock-frequency = <400000>;



	exp1: gpio@20 {

		compatible = "ti,tca6416";

		reg = <0x20>;

		gpio-controller;

		#gpio-cells = <2>;

	};



	exp2: gpio@22 {

		compatible = "ti,tca6424";

		reg = <0x22>;

		gpio-controller;

		#gpio-cells = <2>;

	};

};



&main_i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_i2c1_pins_default>;

	clock-frequency = <400000>;



	exp4: gpio@20 {

		compatible = "ti,tca6408";

		reg = <0x20>;

		gpio-controller;

		#gpio-cells = <2>;

	};

};



&main_sdhci0 {

	/* eMMC */

	non-removable;

	ti,driver-strength-ohm = <50>;

	disable-wp;

};



&main_sdhci1 {

	/* SD card */

	pinctrl-0 = <&main_mmc1_pins_default>;

	pinctrl-names = "default";

	ti,driver-strength-ohm = <50>;

	disable-wp;

};



&serdes_ln_ctrl {

	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,

		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;

};



&usb_serdes_mux {

	idle-states = <1>; /* USB0 to SERDES lane 3 */

};



&usbss0 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_usbss0_pins_default>;

	ti,vbus-divider;

	ti,usb2-only;

};



&usb0 {

	dr_mode = "otg";

	maximum-speed = "high-speed";

};

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