arm64: dts: ti: k3-j7200-common-proc-board: Add USB support (bbcb0522) · Commits · 戴 / test

The board uses lane 3 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that upto 2 protocols can be used at a time. The SERDES is wired for PCIe, QSGMII and USB super-speed. It has been chosen to use PCI2 and QSGMII as default. So restrict USB0 to high-speed mode. Signed-off-by:

Roger Quadros <rogerq@ti.com> Signed-off-by:

Nishanth Menon <nm@ti.com> Reviewed-by:

Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

+22 −0

Original line number	Diff line number	Diff line
		@@ -69,6 +69,12 @@
		J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
		>;
		};

		main_usbss0_pins_default: main-usbss0-pins-default {
		pinctrl-single,pins = <
		J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
		>;
		};
		};

		&wkup_uart0 {
		@@ -191,3 +197,19 @@
		idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
		<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
		};

		&usb_serdes_mux {
		idle-states = <1>; /* USB0 to SERDES lane 3 */
		};

		&usbss0 {
		pinctrl-names = "default";
		pinctrl-0 = <&main_usbss0_pins_default>;
		ti,vbus-divider;
		ti,usb2-only;
		};

		&usb0 {
		dr_mode = "otg";
		maximum-speed = "high-speed";
		};

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