Commit ed0df3ce authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v4.17-rockchip-clk-1' of... 

Merge tag 'v4.17-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

The rk3328 got the most love this time, preparing it for supplying actual
display output in the future and actually protecting all necessary clocks.
The rk3399 simply got a special 1.6GHz rate that is going to be needed
for a board and the core code got a fix to actually free allocated memory
in error case as well as making sure the clock-phases don't return bad
values and stay the same on rate changes.

* tag 'v4.17-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: Add 1.6GHz PLL rate for rk3399
  clk: rockchip: Restore the clock phase after the rate was changed
  clk: rockchip: Prevent calculating mmc phase if clock rate is zero
  clk: rockchip: Free the memory on the error path
  clk: rockchip: document hdmi_phy external input for rk3328
  clk: rockchip: add flags for rk3328 dclk_lcdc
  clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks
  clk: rockchip: protect all remaining rk3328 interconnect clocks
  clk: rockchip: export sclk_hdmi_sfc on rk3328
  clk: rockchip: remove HCLK_VIO from rk3328 dt header
  clk: rockchip: fix hclk_vio_niu on rk3328
parents 7928b2cb 4ee3fd4a

Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt

+1 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ clock-output-names: 
 - "clkin_i2s" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional

 - "phy_50m_out" - output clock of the pll in the mac phy

 - "hdmi_phy" - output clock of the hdmi phy pll - optional



Example: Clock controller node:

drivers/clk/rockchip/clk-mmc-phase.c

+61 −1
Original line number Diff line number Diff line
@@ -25,6 +25,8 @@ struct rockchip_mmc_clock { 
	void __iomem	*reg;

	int		id;

	int		shift;

	int		cached_phase;

	struct notifier_block clk_rate_change_nb;

};



#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
@@ -58,6 +60,12 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) 
	u16 degrees;

	u32 delay_num = 0;



	/* See the comment for rockchip_mmc_set_phase below */

	if (!rate) {

		pr_err("%s: invalid clk rate\n", __func__);

		return -EINVAL;

	}



	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);



	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
@@ -84,6 +92,23 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) 
	u32 raw_value;

	u32 delay;



	/*

	 * The below calculation is based on the output clock from

	 * MMC host to the card, which expects the phase clock inherits

	 * the clock rate from its parent, namely the output clock

	 * provider of MMC host. However, things may go wrong if

	 * (1) It is orphan.

	 * (2) It is assigned to the wrong parent.

	 *

	 * This check help debug the case (1), which seems to be the

	 * most likely problem we often face and which makes it difficult

	 * for people to debug unstable mmc tuning results.

	 */

	if (!rate) {

		pr_err("%s: invalid clk rate\n", __func__);

		return -EINVAL;

	}



	nineties = degrees / 90;

	remainder = (degrees % 90);
@@ -139,6 +164,29 @@ static const struct clk_ops rockchip_mmc_clk_ops = { 
	.set_phase	= rockchip_mmc_set_phase,

};



#define to_rockchip_mmc_clock(x) \

	container_of(x, struct rockchip_mmc_clock, clk_rate_change_nb)

static int rockchip_mmc_clk_rate_notify(struct notifier_block *nb,

					unsigned long event, void *data)

{

	struct rockchip_mmc_clock *mmc_clock = to_rockchip_mmc_clock(nb);



	/*

	 * rockchip_mmc_clk is mostly used by mmc controllers to sample

	 * the intput data, which expects the fixed phase after the tuning

	 * process. However if the clock rate is changed, the phase is stale

	 * and may break the data sampling. So here we try to restore the phase

	 * for that case.

	 */

	if (event == PRE_RATE_CHANGE)

		mmc_clock->cached_phase =

			rockchip_mmc_get_phase(&mmc_clock->hw);

	else if (event == POST_RATE_CHANGE)

		rockchip_mmc_set_phase(&mmc_clock->hw, mmc_clock->cached_phase);



	return NOTIFY_DONE;

}



struct clk *rockchip_clk_register_mmc(const char *name,

				const char *const *parent_names, u8 num_parents,

				void __iomem *reg, int shift)
@@ -146,6 +194,7 @@ struct clk *rockchip_clk_register_mmc(const char *name, 
	struct clk_init_data init;

	struct rockchip_mmc_clock *mmc_clock;

	struct clk *clk;

	int ret;



	mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);

	if (!mmc_clock)
@@ -163,7 +212,18 @@ struct clk *rockchip_clk_register_mmc(const char *name, 


	clk = clk_register(NULL, &mmc_clock->hw);

	if (IS_ERR(clk))

		kfree(mmc_clock);

		goto err_register;



	mmc_clock->clk_rate_change_nb.notifier_call =

				&rockchip_mmc_clk_rate_notify;

	ret = clk_notifier_register(clk, &mmc_clock->clk_rate_change_nb);

	if (ret)

		goto err_notifier;



	return clk;

err_notifier:

	clk_unregister(clk);

err_register:

	kfree(mmc_clock);

	return clk;

}

drivers/clk/rockchip/clk-rk3328.c

+43 −24
Original line number Diff line number Diff line
@@ -304,7 +304,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,

			RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,

			RK3328_CLKGATE_CON(7), 1, GFLAGS),

	GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,

	GATE(0, "aclk_core_niu", "aclk_core", 0,

			RK3328_CLKGATE_CON(13), 0, GFLAGS),

	GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,

			RK3328_CLKGATE_CON(13), 1, GFLAGS),
@@ -318,7 +318,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(6), 6, GFLAGS),

	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,

			RK3328_CLKGATE_CON(14), 0, GFLAGS),

	GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,

	GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,

			RK3328_CLKGATE_CON(14), 1, GFLAGS),



	/* PD_DDR */
@@ -513,9 +513,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(24), 0, GFLAGS),

	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,

			RK3328_CLKGATE_CON(24), 1, GFLAGS),

	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED,

	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,

			RK3328_CLKGATE_CON(24), 2, GFLAGS),

	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED,

	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,

			RK3328_CLKGATE_CON(24), 3, GFLAGS),



	COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
@@ -535,9 +535,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(23), 0, GFLAGS),

	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,

			RK3328_CLKGATE_CON(23), 1, GFLAGS),

	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED,

	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,

			RK3328_CLKGATE_CON(23), 2, GFLAGS),

	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IGNORE_UNUSED,

	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,

			RK3328_CLKGATE_CON(23), 3, GFLAGS),



	COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
@@ -545,9 +545,9 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(6), 3, GFLAGS),

	FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,

			RK3328_CLKGATE_CON(11), 4, GFLAGS),

	GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", CLK_IGNORE_UNUSED,

	GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,

			RK3328_CLKGATE_CON(25), 0, GFLAGS),

	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", CLK_IGNORE_UNUSED,

	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,

			RK3328_CLKGATE_CON(25), 1, GFLAGS),

	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,

			RK3328_CLKGATE_CON(25), 0, GFLAGS),
@@ -588,7 +588,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,

			RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3328_CLKGATE_CON(5), 5, GFLAGS),

	GATE(0, "clk_hdmi_sfc", "xin24m", 0,

	GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,

			RK3328_CLKGATE_CON(5), 4, GFLAGS),



	COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
@@ -602,7 +602,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
			RK3328_CLKGATE_CON(5), 6, GFLAGS),

	DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,

			RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),

	MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, 0,

	MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,

			RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),



	/*
@@ -709,14 +709,14 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 


	/* PD_VOP */

	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),

	GATE(0, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 3, GFLAGS),

	GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),

	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),

	GATE(0, "aclk_vop_niu", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 4, GFLAGS),

	GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),



	GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),

	GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),

	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),

	GATE(0, "aclk_vio_niu", "aclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(22), 2, GFLAGS),

	GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),



	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),

	GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
@@ -724,10 +724,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),

	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),

	GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),

	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 13, GFLAGS),

	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 14, GFLAGS),

	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),

	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),

	GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),

	GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),

	GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),

	GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),

	GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
@@ -743,19 +743,19 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),

	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),

	GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),

	GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 12, GFLAGS),

	GATE(0, "pclk_peri_niu", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 13, GFLAGS),

	GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),

	GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),



	/* PD_GMAC */

	GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),

	GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),

	GATE(0, "aclk_gmac_niu", "aclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 4, GFLAGS),

	GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),

	GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),

	GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),

	GATE(0, "pclk_gmac_niu", "pclk_gmac", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(26), 5, GFLAGS),

	GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),



	/* PD_BUS */

	GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 12, GFLAGS),

	GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),

	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),

	GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),

	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
@@ -769,10 +769,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),

	GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),

	GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),

	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 13, GFLAGS),

	GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),

	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),



	GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 14, GFLAGS),

	GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),

	GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),

	GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),

	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
@@ -807,7 +807,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 
	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS),

	GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),

	GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),

	GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 15, GFLAGS),

	GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),



	/* PD_MMC */

	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc",
@@ -833,11 +833,16 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { 


static const char *const rk3328_critical_clocks[] __initconst = {

	"aclk_bus",

	"aclk_bus_niu",

	"pclk_bus",

	"pclk_bus_niu",

	"hclk_bus",

	"hclk_bus_niu",

	"aclk_peri",

	"hclk_peri",

	"hclk_peri_niu",

	"pclk_peri",

	"pclk_peri_niu",

	"pclk_dbg",

	"aclk_core_niu",

	"aclk_gic400",
@@ -861,6 +866,20 @@ static const char *const rk3328_critical_clocks[] __initconst = { 
	"aclk_rga_niu",

	"pclk_vio_h2p",

	"hclk_vio_h2p",

	"aclk_vio_niu",

	"hclk_vio_niu",

	"aclk_vop_niu",

	"hclk_vop_niu",

	"aclk_gpu_niu",

	"aclk_rkvdec_niu",

	"hclk_rkvdec_niu",

	"aclk_vpu_niu",

	"hclk_vpu_niu",

	"aclk_rkvenc_niu",

	"hclk_rkvenc_niu",

	"aclk_gmac_niu",

	"pclk_gmac_niu",

	"pclk_phy_niu",

};



static void __init rk3328_clk_init(struct device_node *np)

drivers/clk/rockchip/clk-rk3399.c

+1 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { 
	RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),

	RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),

	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),

	RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),

	RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),

	RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),

	RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),

drivers/clk/rockchip/clk.c

+18 −4
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
	struct clk_divider *div = NULL;

	const struct clk_ops *mux_ops = NULL, *div_ops = NULL,

			     *gate_ops = NULL;

	int ret;



	if (num_parents > 1) {

		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
@@ -74,8 +75,10 @@ static struct clk *rockchip_clk_register_branch(const char *name, 


	if (gate_offset >= 0) {

		gate = kzalloc(sizeof(*gate), GFP_KERNEL);

		if (!gate)

		if (!gate) {

			ret = -ENOMEM;

			goto err_gate;

		}



		gate->flags = gate_flags;

		gate->reg = base + gate_offset;
@@ -86,8 +89,10 @@ static struct clk *rockchip_clk_register_branch(const char *name, 


	if (div_width > 0) {

		div = kzalloc(sizeof(*div), GFP_KERNEL);

		if (!div)

		if (!div) {

			ret = -ENOMEM;

			goto err_div;

		}



		div->flags = div_flags;

		div->reg = base + muxdiv_offset;
@@ -106,12 +111,19 @@ static struct clk *rockchip_clk_register_branch(const char *name, 
				     gate ? &gate->hw : NULL, gate_ops,

				     flags);



	if (IS_ERR(clk)) {

		ret = PTR_ERR(clk);

		goto err_composite;

	}



	return clk;

err_composite:

	kfree(div);

err_div:

	kfree(gate);

err_gate:

	kfree(mux);

	return ERR_PTR(-ENOMEM);

	return ERR_PTR(ret);

}



struct rockchip_clk_frac {
@@ -291,8 +303,10 @@ static struct clk *rockchip_clk_register_frac_branch( 
		init.num_parents = child->num_parents;



		mux_clk = clk_register(NULL, &frac_mux->hw);

		if (IS_ERR(mux_clk))

		if (IS_ERR(mux_clk)) {

			kfree(frac);

			return clk;

		}



		rockchip_clk_add_lookup(ctx, mux_clk, child->id);

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