Commit 4ee3fd4a authored Mar 13, 2018 by Derek Basehore Committed by Heiko Stuebner Mar 14, 2018

clk: rockchip: Add 1.6GHz PLL rate for rk3399



We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

parent 60cf09e4

drivers/clk/rockchip/clk-rk3399.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
		RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
		RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
		RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
		RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
		RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
		RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
		RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),

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