Commit ec84c3f6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "Nothing earth-shattering, really - some CPU errata workarounds (one
  day they'll get it right, ha!) and a fix for a boot failure with very
  large kernel images where the alternative patching gets confused when
  patching relative branches using veneers.

   - Fix alternative patching for very large kernel images and modules

   - Hook up existing CPU errata workarounds for Qualcomm Kryo CPUs"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
  arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
  arm64: Add MIDR value for KRYO4XX gold CPU cores
  arm64/alternatives: use subsections for replacement sequences
parents 35e884f8 9b23d95c

Documentation/arm64/silicon-errata.rst

+8 −0
Original line number Diff line number Diff line
@@ -147,6 +147,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| Qualcomm Tech. | Kryo4xx Silver  | N/A             | ARM64_ERRATUM_1024718       |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/include/asm/alternative.h

+8 −8
Original line number Diff line number Diff line
@@ -73,11 +73,11 @@ static inline void apply_alternatives_module(void *start, size_t length) { } 
	".pushsection .altinstructions,\"a\"\n"				\

	ALTINSTR_ENTRY(feature)						\

	".popsection\n"							\

	".pushsection .altinstr_replacement, \"a\"\n"			\

	".subsection 1\n"						\

	"663:\n\t"							\

	newinstr "\n"							\

	"664:\n\t"							\

	".popsection\n\t"						\

	".previous\n\t"							\

	".org	. - (664b-663b) + (662b-661b)\n\t"			\

	".org	. - (662b-661b) + (664b-663b)\n"			\

	".endif\n"
@@ -117,9 +117,9 @@ static inline void apply_alternatives_module(void *start, size_t length) { } 
662:	.pushsection .altinstructions, "a"

	altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f

	.popsection

	.pushsection .altinstr_replacement, "ax"

	.subsection 1

663:	\insn2

664:	.popsection

664:	.previous

	.org	. - (664b-663b) + (662b-661b)

	.org	. - (662b-661b) + (664b-663b)

	.endif
@@ -160,7 +160,7 @@ static inline void apply_alternatives_module(void *start, size_t length) { } 
	.pushsection .altinstructions, "a"

	altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f

	.popsection

	.pushsection .altinstr_replacement, "ax"

	.subsection 1

	.align 2	/* So GAS knows label 661 is suitably aligned */

661:

.endm
@@ -179,9 +179,9 @@ static inline void apply_alternatives_module(void *start, size_t length) { } 
.macro alternative_else

662:

	.if .Lasm_alt_mode==0

	.pushsection .altinstr_replacement, "ax"

	.subsection 1

	.else

	.popsection

	.previous

	.endif

663:

.endm
@@ -192,7 +192,7 @@ static inline void apply_alternatives_module(void *start, size_t length) { } 
.macro alternative_endif

664:

	.if .Lasm_alt_mode==0

	.popsection

	.previous

	.endif

	.org	. - (664b-663b) + (662b-661b)

	.org	. - (662b-661b) + (664b-663b)

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define QCOM_CPU_PART_FALKOR		0xC00

#define QCOM_CPU_PART_KRYO		0x200

#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803

#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804

#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805



#define NVIDIA_CPU_PART_DENVER		0x003
@@ -114,6 +115,7 @@ 
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)

#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)

#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)

#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

arch/arm64/kernel/cpu_errata.c

+15 −6
Original line number Diff line number Diff line
@@ -472,12 +472,7 @@ static bool 
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,

			       int scope)

{

	u32 midr = read_cpuid_id();

	/* Cortex-A76 r0p0 - r3p1 */

	struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);



	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();

	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();

}

#endif
@@ -728,6 +723,8 @@ static const struct midr_range erratum_1418040_list[] = { 
	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),

	/* Neoverse-N1 r0p0 to r3p1 */

	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),

	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */

	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),

	{},

};

#endif
@@ -772,11 +769,22 @@ static const struct midr_range erratum_speculative_at_list[] = { 
#ifdef CONFIG_ARM64_ERRATUM_1530923

	/* Cortex A55 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),

	/* Kryo4xx Silver (rdpe => r1p0) */

	MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),

#endif

	{},

};

#endif



#ifdef CONFIG_ARM64_ERRATUM_1463225

static const struct midr_range erratum_1463225[] = {

	/* Cortex-A76 r0p0 - r3p1 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),

	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */

	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -916,6 +924,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_1463225,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = has_cortex_a76_erratum_1463225,

		.midr_range_list = erratum_1463225,

	},

#endif

#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -1408,6 +1408,8 @@ static bool cpu_has_broken_dbm(void) 
	static const struct midr_range cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_1024718

		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0

		/* Kryo4xx Silver (rdpe => r1p0) */

		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),

#endif

		{},

	};

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