Commit ec7a9318 authored by WANG Xuerui's avatar WANG Xuerui Committed by Thomas Bogendoerfer
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MIPS: emulate CPUCFG instruction on older Loongson64 cores 



CPUCFG is the instruction for querying processor characteristics on
newer Loongson processors, much like CPUID of x86. Since the instruction
is supposedly designed to provide a unified way to do feature detection
(without having to, for example, parse /proc/cpuinfo which is too
heavyweight), it is important to provide compatibility for older cores
without native support. Fortunately, most of the fields can be
synthesized without changes to semantics. Performance is not really big
a concern, because feature detection logic is not expected to be
invoked very often in typical userland applications.

The instruction can't be emulated on LOONGSON_2EF cores, according to
FlyGoat's experiments. Because the LWC2 opcode is assigned to other
valid instructions on 2E and 2F, no RI exception is raised for us to
intercept. So compatibility is only extended back furthest to
Loongson-3A1000. Loongson-2K is covered too, as it is basically a remix
of various blocks from the 3A/3B models from a kernel perspective.

This is lightly based on Loongson's work on their Linux 3.10 fork, for
being the authority on the right feature flags to fill in, where things
aren't otherwise discoverable.

Signed-off-by: default avatarWANG Xuerui <git@xen0n.name>
Reviewed-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 8267e78f

arch/mips/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -1441,6 +1441,18 @@ config CPU_LOONGSON3_WORKAROUNDS 


	  If unsure, please say Y.



config CPU_LOONGSON3_CPUCFG_EMULATION

	bool "Emulate the CPUCFG instruction on older Loongson cores"

	default y

	depends on CPU_LOONGSON64

	help

	  Loongson-3A R4 and newer have the CPUCFG instruction available for

	  userland to query CPU capabilities, much like CPUID on x86. This

	  option provides emulation of the instruction on older Loongson

	  cores, back to Loongson-3A1000.



	  If unsure, please say Y.



config CPU_LOONGSON2E

	bool "Loongson 2E"

	depends on SYS_HAS_CPU_LOONGSON2E

arch/mips/include/asm/cpu-info.h

+9 −0
Original line number Diff line number Diff line
@@ -105,6 +105,15 @@ struct cpuinfo_mips { 
	unsigned int		gtoffset_mask;

	unsigned int		guestid_mask;

	unsigned int		guestid_cache;



#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION

	/* CPUCFG data for this CPU, synthesized at probe time.

	 *

	 * CPUCFG select 0 is PRId, 4 and above are unimplemented for now.

	 * So the only stored values are for CPUCFG selects 1-3 inclusive.

	 */

	u32 loongson3_cpucfg_data[3];

#endif

} __attribute__((aligned(SMP_CACHE_BYTES)));



extern struct cpuinfo_mips cpu_data[];

arch/mips/include/asm/mach-loongson64/cpucfg-emul.h

0 → 100644
+63 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

#ifndef _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_

#define _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_



#include <asm/cpu-info.h>



#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION



#include <loongson_regs.h>



#define LOONGSON_FPREV_MASK 0x7



void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c);



static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,

	__u64 sel)

{

	switch (sel) {

	case LOONGSON_CFG0:

		return c->processor_id;

	case LOONGSON_CFG1:

	case LOONGSON_CFG2:

	case LOONGSON_CFG3:

		return c->loongson3_cpucfg_data[sel - 1];

	case LOONGSON_CFG4:

	case LOONGSON_CFG5:

		/* CPUCFG selects 4 and 5 are related to the input clock

		 * signal.

		 *

		 * Unimplemented for now.

		 */

		return 0;

	case LOONGSON_CFG6:

		/* CPUCFG select 6 is for the undocumented Safe Extension. */

		return 0;

	case LOONGSON_CFG7:

		/* CPUCFG select 7 is for the virtualization extension.

		 * We don't know if the two currently known features are

		 * supported on older cores according to the public

		 * documentation, so leave this at zero.

		 */

		return 0;

	}



	/*

	 * Return 0 for unrecognized CPUCFG selects, which is real hardware

	 * behavior observed on Loongson 3A R4.

	 */

	return 0;

}

#else

static inline void loongson3_cpucfg_synthesize_data(struct cpuinfo_mips *c)

{

}



static inline u32 loongson3_cpucfg_read_synthesized(struct cpuinfo_mips *c,

	__u64 sel)

{

	return 0;

}

#endif



#endif /* _ASM_MACH_LOONGSON64_CPUCFG_EMUL_H_ */

arch/mips/kernel/cpu-probe.c

+9 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
#include <asm/spram.h>

#include <linux/uaccess.h>



#include <asm/mach-loongson64/cpucfg-emul.h>



/* Hardware capabilities */

unsigned int elf_hwcap __read_mostly;

EXPORT_SYMBOL_GPL(elf_hwcap);
@@ -2400,6 +2402,13 @@ void cpu_probe(void) 


	cpu_probe_vmbits(c);



	/* Synthesize CPUCFG data if running on Loongson processors;

	 * no-op otherwise.

	 *

	 * This looks at previously probed features, so keep this at bottom.

	 */

	loongson3_cpucfg_synthesize_data(c);



#ifdef CONFIG_64BIT

	if (cpu == 0)

		__ua_limit = ~((1ull << cpu_vmbits) - 1);

arch/mips/kernel/traps.c

+45 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ 
#include <asm/tlbex.h>

#include <asm/uasm.h>



#include <asm/mach-loongson64/cpucfg-emul.h>



extern void check_wait(void);

extern asmlinkage void rollback_handle_int(void);

extern asmlinkage void handle_int(void);
@@ -693,6 +695,44 @@ static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 
	return -1;			/* Must be something else ... */

}



/*

 * Loongson-3 CSR instructions emulation

 */



#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION



#define LWC2             0xc8000000

#define RS               BASE

#define CSR_OPCODE2      0x00000118

#define CSR_OPCODE2_MASK 0x000007ff

#define CSR_FUNC_MASK    RT

#define CSR_FUNC_CPUCFG  0x8



static int simulate_loongson3_cpucfg(struct pt_regs *regs,

				     unsigned int opcode)

{

	int op = opcode & OPCODE;

	int op2 = opcode & CSR_OPCODE2_MASK;

	int csr_func = (opcode & CSR_FUNC_MASK) >> 16;



	if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {

		int rd = (opcode & RD) >> 11;

		int rs = (opcode & RS) >> 21;

		__u64 sel = regs->regs[rs];



		perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);



		regs->regs[rd] = loongson3_cpucfg_read_synthesized(

			&current_cpu_data, sel);



		return 0;

	}



	/* Not ours.  */

	return -1;

}

#endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */



asmlinkage void do_ov(struct pt_regs *regs)

{

	enum ctx_state prev_state;
@@ -1166,6 +1206,11 @@ no_r2_instr: 


		if (status < 0)

			status = simulate_fp(regs, opcode, old_epc, old31);



#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION

		if (status < 0)

			status = simulate_loongson3_cpucfg(regs, opcode);

#endif

	} else if (cpu_has_mmips) {

		unsigned short mmop[2] = { 0 };

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