Commit 8267e78f authored by Huacai Chen's avatar Huacai Chen Committed by Thomas Bogendoerfer
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MIPS: Tidy up CP0.Config6 bits definition 



CP0.Config6 is a Vendor-defined register whose bits definitions are
different from one to another. Recently, Xuerui's Loongson-3 patch and
Serge's P5600 patch make the definitions inconsistency and unclear.

To make life easy, this patch tidy the definition up:
1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
3, Add bit6/bit7 definition for Loongson-3 which will be used later.

All existing users of these macros are updated.

Cc: WANG Xuerui <git@xen0n.name>
Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 41528ba6

arch/mips/include/asm/mipsregs.h

+24 −13
Original line number Diff line number Diff line
@@ -686,27 +686,38 @@ 
#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)

#define MIPS_CONF5_K		(_ULCAST_(1) << 30)



/* Config6 feature bits for proAptiv/P5600 */



/* Jump register cache prediction disable */

#define MIPS_CONF6_JRCD		(_ULCAST_(1) << 0)

#define MIPS_CONF6_MTI_JRCD		(_ULCAST_(1) << 0)

/* MIPSr6 extensions enable */

#define MIPS_CONF6_R6		(_ULCAST_(1) << 2)

#define MIPS_CONF6_MTI_R6		(_ULCAST_(1) << 2)

/* IFU Performance Control */

#define MIPS_CONF6_IFUPERFCTL	(_ULCAST_(3) << 10)

#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)

#define MIPS_CONF6_MTI_IFUPERFCTL	(_ULCAST_(3) << 10)

#define MIPS_CONF6_MTI_SYND		(_ULCAST_(1) << 13)

/* Sleep state performance counter disable */

#define MIPS_CONF6_SPCD		(_ULCAST_(1) << 14)

#define MIPS_CONF6_MTI_SPCD		(_ULCAST_(1) << 14)

/* proAptiv FTLB on/off bit */

#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)

#define MIPS_CONF6_MTI_FTLBEN		(_ULCAST_(1) << 15)

/* Disable load/store bonding */

#define MIPS_CONF6_DLSB		(_ULCAST_(1) << 21)

/* Loongson-3 FTLB on/off bit */

#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)

#define MIPS_CONF6_MTI_DLSB		(_ULCAST_(1) << 21)

/* FTLB probability bits */

#define MIPS_CONF6_FTLBP_SHIFT	(16)

/* Loongson-3 feature bits */

#define MIPS_CONF6_LOONGSON_SCRAND	(_ULCAST_(1) << 17)

#define MIPS_CONF6_MTI_FTLBP_SHIFT	(16)



/* Config6 feature bits for Loongson-3 */



/* Loongson-3 internal timer bit */

#define MIPS_CONF6_LOONGSON_INTIMER	(_ULCAST_(1) << 6)

/* Loongson-3 external timer bit */

#define MIPS_CONF6_LOONGSON_EXTIMER	(_ULCAST_(1) << 7)

/* Loongson-3 SFB on/off bit, STFill in manual */

#define MIPS_CONF6_LOONGSON_SFBEN	(_ULCAST_(1) << 8)

/* Loongson-3's LL on exclusive cacheline */

#define MIPS_CONF6_LOONGSON_LLEXC	(_ULCAST_(1) << 16)

#define MIPS_CONF6_LOONGSON_STFILL	(_ULCAST_(1) << 8)

/* Loongson-3's SC has a random delay */

#define MIPS_CONF6_LOONGSON_SCRAND	(_ULCAST_(1) << 17)

/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */

#define MIPS_CONF6_LOONGSON_FTLBDIS	(_ULCAST_(1) << 22)



#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)

arch/mips/kernel/cpu-probe.c

+6 −6
Original line number Diff line number Diff line
@@ -633,14 +633,14 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 
		config = read_c0_config6();



		if (flags & FTLB_EN)

			config |= MIPS_CONF6_FTLBEN;

			config |= MIPS_CONF6_MTI_FTLBEN;

		else

			config &= ~MIPS_CONF6_FTLBEN;

			config &= ~MIPS_CONF6_MTI_FTLBEN;



		if (flags & FTLB_SET_PROB) {

			config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);

			config &= ~(3 << MIPS_CONF6_MTI_FTLBP_SHIFT);

			config |= calculate_ftlb_probability(c)

				  << MIPS_CONF6_FTLBP_SHIFT;

				  << MIPS_CONF6_MTI_FTLBP_SHIFT;

		}



		write_c0_config6(config);
@@ -660,10 +660,10 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 
		config = read_c0_config6();

		if (flags & FTLB_EN)

			/* Enable FTLB */

			write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);

			write_c0_config6(config & ~MIPS_CONF6_LOONGSON_FTLBDIS);

		else

			/* Disable FTLB */

			write_c0_config6(config | MIPS_CONF6_FTLBDIS);

			write_c0_config6(config | MIPS_CONF6_LOONGSON_FTLBDIS);

		break;

	default:

		return 1;

arch/mips/mm/c-r4k.c

+2 −2
Original line number Diff line number Diff line
@@ -1073,12 +1073,12 @@ static inline int alias_74k_erratum(struct cpuinfo_mips *c) 
		if (rev <= PRID_REV_ENCODE_332(2, 4, 0))

			present = 1;

		if (rev == PRID_REV_ENCODE_332(2, 4, 0))

			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);

			write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);

		break;

	case PRID_IMP_1074K:

		if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {

			present = 1;

			write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);

			write_c0_config6(read_c0_config6() | MIPS_CONF6_MTI_SYND);

		}

		break;

	default:

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