Commit ebb58dc2 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/pmu: rename from pwr (no binary change) 



Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent f3867f43

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ enum nv_subdev_type { 
	NVDEV_SUBDEV_INSTMEM,

	NVDEV_SUBDEV_VM,

	NVDEV_SUBDEV_BAR,

	NVDEV_SUBDEV_PWR,

	NVDEV_SUBDEV_PMU,

	NVDEV_SUBDEV_VOLT,

	NVDEV_SUBDEV_THERM,

	NVDEV_SUBDEV_CLK,

drivers/gpu/drm/nouveau/include/nvkm/subdev/pwr.h→drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h

+17 −17
Original line number Diff line number Diff line 
#ifndef __NOUVEAU_PWR_H__

#define __NOUVEAU_PWR_H__

#ifndef __NOUVEAU_PMU_H__

#define __NOUVEAU_PMU_H__



#include <core/subdev.h>

#include <core/device.h>



struct nouveau_pwr {

struct nouveau_pmu {

	struct nouveau_subdev base;



	struct {
@@ -23,26 +23,26 @@ struct nouveau_pwr { 
		u32 data[2];

	} recv;



	int  (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);

	void (*pgob)(struct nouveau_pwr *, bool);

	int  (*message)(struct nouveau_pmu *, u32[2], u32, u32, u32, u32);

	void (*pgob)(struct nouveau_pmu *, bool);

};



static inline struct nouveau_pwr *

nouveau_pwr(void *obj)

static inline struct nouveau_pmu *

nouveau_pmu(void *obj)

{

	return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PWR);

	return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_PMU);

}



extern struct nouveau_oclass *nva3_pwr_oclass;

extern struct nouveau_oclass *nvc0_pwr_oclass;

extern struct nouveau_oclass *nvd0_pwr_oclass;

extern struct nouveau_oclass *gk104_pwr_oclass;

extern struct nouveau_oclass *nv108_pwr_oclass;

extern struct nouveau_oclass *gk20a_pwr_oclass;

extern struct nouveau_oclass *nva3_pmu_oclass;

extern struct nouveau_oclass *nvc0_pmu_oclass;

extern struct nouveau_oclass *nvd0_pmu_oclass;

extern struct nouveau_oclass *gk104_pmu_oclass;

extern struct nouveau_oclass *nv108_pmu_oclass;

extern struct nouveau_oclass *gk20a_pmu_oclass;



/* interface to MEMX process running on PPWR */

/* interface to MEMX process running on PMU */

struct nouveau_memx;

int  nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **);

int  nouveau_memx_init(struct nouveau_pmu *, struct nouveau_memx **);

int  nouveau_memx_fini(struct nouveau_memx **, bool exec);

void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);

void nouveau_memx_wait(struct nouveau_memx *,
@@ -50,7 +50,7 @@ void nouveau_memx_wait(struct nouveau_memx *, 
void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);

void nouveau_memx_wait_vblank(struct nouveau_memx *);

void nouveau_memx_train(struct nouveau_memx *);

int  nouveau_memx_train_result(struct nouveau_pwr *, u32 *, int);

int  nouveau_memx_train_result(struct nouveau_pmu *, u32 *, int);

void nouveau_memx_block(struct nouveau_memx *);

void nouveau_memx_unblock(struct nouveau_memx *);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+1 −1
Original line number Diff line number Diff line
@@ -222,7 +222,7 @@ static const u64 disable_map[] = { 
	[NVDEV_SUBDEV_BAR]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_SUBDEV_VOLT]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_SUBDEV_THERM]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_SUBDEV_PWR]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_SUBDEV_PMU]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_SUBDEV_FUSE]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_ENGINE_DMAOBJ]	= NV_DEVICE_V0_DISABLE_CORE,

	[NVDEV_ENGINE_PERFMON]  = NV_DEVICE_V0_DISABLE_CORE,

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

+3 −3
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#include <subdev/instmem.h>

#include <subdev/vm.h>

#include <subdev/bar.h>

#include <subdev/pwr.h>

#include <subdev/pmu.h>

#include <subdev/volt.h>



#include <engine/device.h>
@@ -77,7 +77,7 @@ gm100_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;



#if 0

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -121,7 +121,7 @@ gm100_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nv108_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nv108_pmu_oclass;

#if 0

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

#endif

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

+5 −5
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
#include <subdev/instmem.h>

#include <subdev/vm.h>

#include <subdev/bar.h>

#include <subdev/pwr.h>

#include <subdev/pmu.h>

#include <subdev/volt.h>



#include <engine/device.h>
@@ -362,7 +362,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -393,7 +393,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -423,7 +423,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;
@@ -453,7 +453,7 @@ nv50_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_VM     ] = &nv50_vmmgr_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &nv50_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PWR    ] =  nva3_pwr_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  nva3_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv84_fifo_oclass;

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