Commit eacf2104 authored by Chris Wilson's avatar Chris Wilson Committed by Joonas Lahtinen
Browse files

drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds 



Rescue the GT workarounds from being buried inside init_clock_gating so
that we remember to apply them after a GT reset, and that they are
included in our verification that the workarounds are applied.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200611080140.30228-5-chris@chris-wilson.co.uk


(cherry picked from commit 806a45c0)
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent fd2599bd

drivers/gpu/drm/i915/gt/intel_workarounds.c

+14 −0
Original line number Diff line number Diff line
@@ -692,6 +692,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) 
	return 0;

}



static void

ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{

	wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);



	/* WaDisableRenderCachePipelinedFlush:ilk */

	wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);



	/* WaDisable_RenderCache_OperationalFlush:ilk */

	wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);

}



static void

snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)

{
@@ -1173,6 +1185,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 
		ivb_gt_workarounds_init(i915, wal);

	else if (IS_GEN(i915, 6))

		snb_gt_workarounds_init(i915, wal);

	else if (IS_GEN(i915, 5))

		ilk_gt_workarounds_init(i915, wal);

	else if (INTEL_GEN(i915) <= 8)

		return;

	else

drivers/gpu/drm/i915/intel_pm.c

+0 −10
Original line number Diff line number Diff line
@@ -6830,16 +6830,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) 
	I915_WRITE(ILK_DISPLAY_CHICKEN2,

		   I915_READ(ILK_DISPLAY_CHICKEN2) |

		   ILK_ELPIN_409_SELECT);

	I915_WRITE(_3D_CHICKEN2,

		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |

		   _3D_CHICKEN2_WM_READ_PIPELINED);



	/* WaDisableRenderCachePipelinedFlush:ilk */

	I915_WRITE(CACHE_MODE_0,

		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));



	/* WaDisable_RenderCache_OperationalFlush:ilk */

	I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));



	g4x_disable_trickle_feed(dev_priv);

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