clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based (ea6a723a) · Commits · 戴 / test

drivers/clk/imx/clk-divider-gate.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -173,7 +173,7 @@ static const struct clk_ops clk_divider_gate_ops = {
		* default as our HW is. Besides that it supports only CLK_DIVIDER_READ_ONLY
		* flag which can be specified by user flexibly.
		*/
		struct clk_hw imx_clk_divider_gate(const char name, const char *parent_name,
		struct clk_hw imx_clk_hw_divider_gate(const char name, const char *parent_name,
		unsigned long flags, void __iomem *reg,
		u8 shift, u8 width, u8 clk_divider_flags,
		const struct clk_div_table *table,

drivers/clk/imx/clk-imx7ulp.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -111,7 +111,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
		clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT \| CLK_SET_PARENT_GATE);
		clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT \| CLK_SET_PARENT_GATE);

		clks[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);
		clks[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);

		/* scs/ddr/nic select different clock source requires that clock to be enabled first */
		clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
		@@ -122,7 +122,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
		clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
		clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);

		clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL, base + 0x30, 0, 3,
		clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL, base + 0x30, 0, 3,
		0, ulp_div_table, &imx_ccm_lock);

		clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL);
		@@ -131,9 +131,9 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)

		clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);

		clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
		clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
		CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
		clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
		clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
		CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);

		imx_check_clk_hws(clks, clk_data->num);

drivers/clk/imx/clk.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -469,7 +469,7 @@ struct clk imx8m_clk_composite_flags(const char name,
		#define imx8m_clk_composite_critical(name, parent_names, reg) \
		__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)

		struct clk_hw imx_clk_divider_gate(const char name, const char *parent_name,
		struct clk_hw imx_clk_hw_divider_gate(const char name, const char *parent_name,
		unsigned long flags, void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags, const struct clk_div_table *table,
		spinlock_t *lock);

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