Commit 40ad61d6 authored by Abel Vesa's avatar Abel Vesa Committed by Shawn Guo
Browse files

clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based 



Renaming the imx_clk_pfdv2 register function to imx_clk_hw_pfdv2 to be
more obvious it is clk_hw based.

Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 74e63951

drivers/clk/imx/clk-imx7ulp.c

+8 −8
Original line number Diff line number Diff line
@@ -94,16 +94,16 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) 
	clks[IMX7ULP_CLK_SPLL]		= imx_clk_hw_pllv4("spll",  "spll_pre_div", base + 0x600);



	/* APLL PFDs */

	clks[IMX7ULP_CLK_APLL_PFD0]	= imx_clk_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);

	clks[IMX7ULP_CLK_APLL_PFD1]	= imx_clk_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);

	clks[IMX7ULP_CLK_APLL_PFD2]	= imx_clk_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);

	clks[IMX7ULP_CLK_APLL_PFD3]	= imx_clk_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);

	clks[IMX7ULP_CLK_APLL_PFD0]	= imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);

	clks[IMX7ULP_CLK_APLL_PFD1]	= imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);

	clks[IMX7ULP_CLK_APLL_PFD2]	= imx_clk_hw_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);

	clks[IMX7ULP_CLK_APLL_PFD3]	= imx_clk_hw_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);



	/* SPLL PFDs */

	clks[IMX7ULP_CLK_SPLL_PFD0]	= imx_clk_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);

	clks[IMX7ULP_CLK_SPLL_PFD1]	= imx_clk_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);

	clks[IMX7ULP_CLK_SPLL_PFD2]	= imx_clk_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);

	clks[IMX7ULP_CLK_SPLL_PFD3]	= imx_clk_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);

	clks[IMX7ULP_CLK_SPLL_PFD0]	= imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);

	clks[IMX7ULP_CLK_SPLL_PFD1]	= imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);

	clks[IMX7ULP_CLK_SPLL_PFD2]	= imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);

	clks[IMX7ULP_CLK_SPLL_PFD3]	= imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);



	/* PLL Mux */

	clks[IMX7ULP_CLK_APLL_PFD_SEL]	= imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);

drivers/clk/imx/clk-pfdv2.c

+1 −1
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ static const struct clk_ops clk_pfdv2_ops = { 
	.is_enabled     = clk_pfdv2_is_enabled,

};



struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,

struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,

			     void __iomem *reg, u8 idx)

{

	struct clk_init_data init;

drivers/clk/imx/clk.h

+1 −1
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, 
struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,

		void __iomem *reg, u8 idx);



struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,

struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,

			     void __iomem *reg, u8 idx);



struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,

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