Merge tag 'mlx5-updates-2020-05-15' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux (ea6119aa) · Commits · 戴 / test

drivers/net/ethernet/mellanox/mlx5/core/en.h

+3 −51

Original line number	Diff line number	Diff line
		@@ -36,7 +36,6 @@
		#include <linux/etherdevice.h>
		#include <linux/timecounter.h>
		#include <linux/net_tstamp.h>
		#include <linux/ptp_clock_kernel.h>
		#include <linux/crash_dump.h>
		#include <linux/mlx5/driver.h>
		#include <linux/mlx5/qp.h>
		@@ -53,6 +52,7 @@
		#include "wq.h"
		#include "mlx5_core.h"
		#include "en_stats.h"
		#include "en/dcbnl.h"
		#include "en/fs.h"
		#include "lib/hv_vhca.h"

		@@ -69,8 +69,6 @@ struct page_pool;
		#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
		#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))

		#define MLX5E_MAX_PRIORITY 8
		#define MLX5E_MAX_DSCP 64
		#define MLX5E_MAX_NUM_TC 8

		#define MLX5_RX_HEADROOM NET_SKB_PAD
		@@ -243,10 +241,6 @@ enum mlx5e_priv_flag {

		#define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))

		#ifdef CONFIG_MLX5_CORE_EN_DCB
		#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
		#endif

		struct mlx5e_params {
		u8 log_sq_size;
		u8 rq_wq_type;
		@@ -271,42 +265,6 @@ struct mlx5e_params {
		int hard_mtu;
		};

		#ifdef CONFIG_MLX5_CORE_EN_DCB
		struct mlx5e_cee_config {
		/* bw pct for priority group */
		u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
		u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
		bool pfc_setting[CEE_DCBX_MAX_PRIO];
		bool pfc_enable;
		};

		enum {
		MLX5_DCB_CHG_RESET,
		MLX5_DCB_NO_CHG,
		MLX5_DCB_CHG_NO_RESET,
		};

		struct mlx5e_dcbx {
		enum mlx5_dcbx_oper_mode mode;
		struct mlx5e_cee_config cee_cfg; /* pending configuration */
		u8 dscp_app_cnt;

		/* The only setting that cannot be read from FW */
		u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
		u8 cap;

		/* Buffer configuration */
		bool manual_buffer;
		u32 cable_len;
		u32 xoff;
		};

		struct mlx5e_dcbx_dp {
		u8 dscp2prio[MLX5E_MAX_DSCP];
		u8 trust_state;
		};
		#endif

		enum {
		MLX5E_RQ_STATE_ENABLED,
		MLX5E_RQ_STATE_RECOVERING,
		@@ -1069,13 +1027,6 @@ static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
		}

		extern const struct ethtool_ops mlx5e_ethtool_ops;
		#ifdef CONFIG_MLX5_CORE_EN_DCB
		extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
		int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv priv, struct ieee_ets ets);
		void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
		void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
		void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
		#endif

		int mlx5e_create_tir(struct mlx5_core_dev mdev, struct mlx5e_tir tir,
		u32 *in);
		@@ -1083,7 +1034,8 @@ void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
		struct mlx5e_tir *tir);
		int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
		void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
		int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
		int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
		bool enable_mc_lb);

		/* common netdev helpers */
		void mlx5e_create_q_counters(struct mlx5e_priv *priv);

drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h

0 → 100644

+54 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
		/* Copyright (c) 2020 Mellanox Technologies. */

		#ifndef __MLX5E_DCBNL_H__
		#define __MLX5E_DCBNL_H__

		#ifdef CONFIG_MLX5_CORE_EN_DCB

		#define MLX5E_MAX_PRIORITY (8)

		struct mlx5e_cee_config {
		/* bw pct for priority group */
		u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
		u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
		bool pfc_setting[CEE_DCBX_MAX_PRIO];
		bool pfc_enable;
		};

		struct mlx5e_dcbx {
		enum mlx5_dcbx_oper_mode mode;
		struct mlx5e_cee_config cee_cfg; /* pending configuration */
		u8 dscp_app_cnt;

		/* The only setting that cannot be read from FW */
		u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
		u8 cap;

		/* Buffer configuration */
		bool manual_buffer;
		u32 cable_len;
		u32 xoff;
		};

		#define MLX5E_MAX_DSCP (64)

		struct mlx5e_dcbx_dp {
		u8 dscp2prio[MLX5E_MAX_DSCP];
		u8 trust_state;
		};

		void mlx5e_dcbnl_build_netdev(struct net_device *netdev);
		void mlx5e_dcbnl_build_rep_netdev(struct net_device *netdev);
		void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
		void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
		void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
		#else
		static inline void mlx5e_dcbnl_build_netdev(struct net_device *netdev) {}
		static inline void mlx5e_dcbnl_build_rep_netdev(struct net_device *netdev) {}
		static inline void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv) {}
		static inline void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv) {}
		static inline void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv) {}
		#endif

		#endif /* __MLX5E_DCBNL_H__ */

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c

+286 −22

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		#define MLX5_CT_ZONE_MASK GENMASK(MLX5_CT_ZONE_BITS - 1, 0)
		#define MLX5_CT_STATE_ESTABLISHED_BIT BIT(1)
		#define MLX5_CT_STATE_TRK_BIT BIT(2)
		#define MLX5_CT_STATE_NAT_BIT BIT(3)

		#define MLX5_FTE_ID_BITS (mlx5e_tc_attr_to_reg_mappings[FTEID_TO_REG].mlen * 8)
		#define MLX5_FTE_ID_MAX GENMASK(MLX5_FTE_ID_BITS - 1, 0)
		@@ -61,6 +62,15 @@ struct mlx5_ct_zone_rule {
		bool nat;
		};

		struct mlx5_tc_ct_pre {
		struct mlx5_flow_table *fdb;
		struct mlx5_flow_group *flow_grp;
		struct mlx5_flow_group *miss_grp;
		struct mlx5_flow_handle *flow_rule;
		struct mlx5_flow_handle *miss_rule;
		struct mlx5_modify_hdr *modify_hdr;
		};

		struct mlx5_ct_ft {
		struct rhash_head node;
		u16 zone;
		@@ -68,6 +78,8 @@ struct mlx5_ct_ft {
		struct nf_flowtable *nf_ft;
		struct mlx5_tc_ct_priv *ct_priv;
		struct rhashtable ct_entries_ht;
		struct mlx5_tc_ct_pre pre_ct;
		struct mlx5_tc_ct_pre pre_ct_nat;
		};

		struct mlx5_ct_entry {
		@@ -426,6 +438,7 @@ mlx5_tc_ct_entry_create_mod_hdr(struct mlx5_tc_ct_priv *ct_priv,
		struct mlx5_eswitch *esw = ct_priv->esw;
		struct mlx5_modify_hdr *mod_hdr;
		struct flow_action_entry *meta;
		u16 ct_state = 0;
		int err;

		meta = mlx5_tc_ct_get_ct_metadata_action(flow_rule);
		@@ -444,11 +457,13 @@ mlx5_tc_ct_entry_create_mod_hdr(struct mlx5_tc_ct_priv *ct_priv,
		&mod_acts);
		if (err)
		goto err_mapping;

		ct_state \|= MLX5_CT_STATE_NAT_BIT;
		}

		ct_state \|= MLX5_CT_STATE_ESTABLISHED_BIT \| MLX5_CT_STATE_TRK_BIT;
		err = mlx5_tc_ct_entry_set_registers(ct_priv, &mod_acts,
		(MLX5_CT_STATE_ESTABLISHED_BIT \|
		MLX5_CT_STATE_TRK_BIT),
		ct_state,
		meta->ct_metadata.mark,
		meta->ct_metadata.labels[0],
		tupleid);
		@@ -791,6 +806,238 @@ mlx5_tc_ct_parse_action(struct mlx5e_priv *priv,
		return 0;
		}

		static int tc_ct_pre_ct_add_rules(struct mlx5_ct_ft *ct_ft,
		struct mlx5_tc_ct_pre *pre_ct,
		bool nat)
		{
		struct mlx5_tc_ct_priv *ct_priv = ct_ft->ct_priv;
		struct mlx5e_tc_mod_hdr_acts pre_mod_acts = {};
		struct mlx5_core_dev *dev = ct_priv->esw->dev;
		struct mlx5_flow_table *fdb = pre_ct->fdb;
		struct mlx5_flow_destination dest = {};
		struct mlx5_flow_act flow_act = {};
		struct mlx5_modify_hdr *mod_hdr;
		struct mlx5_flow_handle *rule;
		struct mlx5_flow_spec *spec;
		u32 ctstate;
		u16 zone;
		int err;

		spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
		if (!spec)
		return -ENOMEM;

		zone = ct_ft->zone & MLX5_CT_ZONE_MASK;
		err = mlx5e_tc_match_to_reg_set(dev, &pre_mod_acts, ZONE_TO_REG, zone);
		if (err) {
		ct_dbg("Failed to set zone register mapping");
		goto err_mapping;
		}

		mod_hdr = mlx5_modify_header_alloc(dev,
		MLX5_FLOW_NAMESPACE_FDB,
		pre_mod_acts.num_actions,
		pre_mod_acts.actions);

		if (IS_ERR(mod_hdr)) {
		err = PTR_ERR(mod_hdr);
		ct_dbg("Failed to create pre ct mod hdr");
		goto err_mapping;
		}
		pre_ct->modify_hdr = mod_hdr;

		flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST \|
		MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
		flow_act.flags \|= FLOW_ACT_IGNORE_FLOW_LEVEL;
		flow_act.modify_hdr = mod_hdr;
		dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;

		/* add flow rule */
		mlx5e_tc_match_to_reg_match(spec, ZONE_TO_REG,
		zone, MLX5_CT_ZONE_MASK);
		ctstate = MLX5_CT_STATE_TRK_BIT;
		if (nat)
		ctstate \|= MLX5_CT_STATE_NAT_BIT;
		mlx5e_tc_match_to_reg_match(spec, CTSTATE_TO_REG, ctstate, ctstate);

		dest.ft = ct_priv->post_ct;
		rule = mlx5_add_flow_rules(fdb, spec, &flow_act, &dest, 1);
		if (IS_ERR(rule)) {
		err = PTR_ERR(rule);
		ct_dbg("Failed to add pre ct flow rule zone %d", zone);
		goto err_flow_rule;
		}
		pre_ct->flow_rule = rule;

		/* add miss rule */
		memset(spec, 0, sizeof(*spec));
		dest.ft = nat ? ct_priv->ct_nat : ct_priv->ct;
		rule = mlx5_add_flow_rules(fdb, spec, &flow_act, &dest, 1);
		if (IS_ERR(rule)) {
		err = PTR_ERR(rule);
		ct_dbg("Failed to add pre ct miss rule zone %d", zone);
		goto err_miss_rule;
		}
		pre_ct->miss_rule = rule;

		dealloc_mod_hdr_actions(&pre_mod_acts);
		kvfree(spec);
		return 0;

		err_miss_rule:
		mlx5_del_flow_rules(pre_ct->flow_rule);
		err_flow_rule:
		mlx5_modify_header_dealloc(dev, pre_ct->modify_hdr);
		err_mapping:
		dealloc_mod_hdr_actions(&pre_mod_acts);
		kvfree(spec);
		return err;
		}

		static void
		tc_ct_pre_ct_del_rules(struct mlx5_ct_ft *ct_ft,
		struct mlx5_tc_ct_pre *pre_ct)
		{
		struct mlx5_tc_ct_priv *ct_priv = ct_ft->ct_priv;
		struct mlx5_core_dev *dev = ct_priv->esw->dev;

		mlx5_del_flow_rules(pre_ct->flow_rule);
		mlx5_del_flow_rules(pre_ct->miss_rule);
		mlx5_modify_header_dealloc(dev, pre_ct->modify_hdr);
		}

		static int
		mlx5_tc_ct_alloc_pre_ct(struct mlx5_ct_ft *ct_ft,
		struct mlx5_tc_ct_pre *pre_ct,
		bool nat)
		{
		int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
		struct mlx5_tc_ct_priv *ct_priv = ct_ft->ct_priv;
		struct mlx5_core_dev *dev = ct_priv->esw->dev;
		struct mlx5_flow_table_attr ft_attr = {};
		struct mlx5_flow_namespace *ns;
		struct mlx5_flow_table *ft;
		struct mlx5_flow_group *g;
		u32 metadata_reg_c_2_mask;
		u32 *flow_group_in;
		void *misc;
		int err;

		ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
		if (!ns) {
		err = -EOPNOTSUPP;
		ct_dbg("Failed to get FDB flow namespace");
		return err;
		}

		flow_group_in = kvzalloc(inlen, GFP_KERNEL);
		if (!flow_group_in)
		return -ENOMEM;

		ft_attr.flags = MLX5_FLOW_TABLE_UNMANAGED;
		ft_attr.prio = FDB_TC_OFFLOAD;
		ft_attr.max_fte = 2;
		ft_attr.level = 1;
		ft = mlx5_create_flow_table(ns, &ft_attr);
		if (IS_ERR(ft)) {
		err = PTR_ERR(ft);
		ct_dbg("Failed to create pre ct table");
		goto out_free;
		}
		pre_ct->fdb = ft;

		/* create flow group */
		MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
		MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
		MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
		MLX5_MATCH_MISC_PARAMETERS_2);

		misc = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
		match_criteria.misc_parameters_2);

		metadata_reg_c_2_mask = MLX5_CT_ZONE_MASK;
		metadata_reg_c_2_mask \|= (MLX5_CT_STATE_TRK_BIT << 16);
		if (nat)
		metadata_reg_c_2_mask \|= (MLX5_CT_STATE_NAT_BIT << 16);

		MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_2,
		metadata_reg_c_2_mask);

		g = mlx5_create_flow_group(ft, flow_group_in);
		if (IS_ERR(g)) {
		err = PTR_ERR(g);
		ct_dbg("Failed to create pre ct group");
		goto err_flow_grp;
		}
		pre_ct->flow_grp = g;

		/* create miss group */
		memset(flow_group_in, 0, inlen);
		MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
		MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
		g = mlx5_create_flow_group(ft, flow_group_in);
		if (IS_ERR(g)) {
		err = PTR_ERR(g);
		ct_dbg("Failed to create pre ct miss group");
		goto err_miss_grp;
		}
		pre_ct->miss_grp = g;

		err = tc_ct_pre_ct_add_rules(ct_ft, pre_ct, nat);
		if (err)
		goto err_add_rules;

		kvfree(flow_group_in);
		return 0;

		err_add_rules:
		mlx5_destroy_flow_group(pre_ct->miss_grp);
		err_miss_grp:
		mlx5_destroy_flow_group(pre_ct->flow_grp);
		err_flow_grp:
		mlx5_destroy_flow_table(ft);
		out_free:
		kvfree(flow_group_in);
		return err;
		}

		static void
		mlx5_tc_ct_free_pre_ct(struct mlx5_ct_ft *ct_ft,
		struct mlx5_tc_ct_pre *pre_ct)
		{
		tc_ct_pre_ct_del_rules(ct_ft, pre_ct);
		mlx5_destroy_flow_group(pre_ct->miss_grp);
		mlx5_destroy_flow_group(pre_ct->flow_grp);
		mlx5_destroy_flow_table(pre_ct->fdb);
		}

		static int
		mlx5_tc_ct_alloc_pre_ct_tables(struct mlx5_ct_ft *ft)
		{
		int err;

		err = mlx5_tc_ct_alloc_pre_ct(ft, &ft->pre_ct, false);
		if (err)
		return err;

		err = mlx5_tc_ct_alloc_pre_ct(ft, &ft->pre_ct_nat, true);
		if (err)
		goto err_pre_ct_nat;

		return 0;

		err_pre_ct_nat:
		mlx5_tc_ct_free_pre_ct(ft, &ft->pre_ct);
		return err;
		}

		static void
		mlx5_tc_ct_free_pre_ct_tables(struct mlx5_ct_ft *ft)
		{
		mlx5_tc_ct_free_pre_ct(ft, &ft->pre_ct_nat);
		mlx5_tc_ct_free_pre_ct(ft, &ft->pre_ct);
		}

		static struct mlx5_ct_ft *
		mlx5_tc_ct_add_ft_cb(struct mlx5_tc_ct_priv *ct_priv, u16 zone,
		struct nf_flowtable *nf_ft)
		@@ -813,6 +1060,10 @@ mlx5_tc_ct_add_ft_cb(struct mlx5_tc_ct_priv *ct_priv, u16 zone,
		ft->ct_priv = ct_priv;
		refcount_set(&ft->refcount, 1);

		err = mlx5_tc_ct_alloc_pre_ct_tables(ft);
		if (err)
		goto err_alloc_pre_ct;

		err = rhashtable_init(&ft->ct_entries_ht, &cts_ht_params);
		if (err)
		goto err_init;
		@@ -834,6 +1085,8 @@ err_add_cb:
		err_insert:
		rhashtable_destroy(&ft->ct_entries_ht);
		err_init:
		mlx5_tc_ct_free_pre_ct_tables(ft);
		err_alloc_pre_ct:
		kfree(ft);
		return ERR_PTR(err);
		}
		@@ -859,21 +1112,40 @@ mlx5_tc_ct_del_ft_cb(struct mlx5_tc_ct_priv ct_priv, struct mlx5_ct_ft ft)
		rhashtable_free_and_destroy(&ft->ct_entries_ht,
		mlx5_tc_ct_flush_ft_entry,
		ct_priv);
		mlx5_tc_ct_free_pre_ct_tables(ft);
		kfree(ft);
		}

		/* We translate the tc filter with CT action to the following HW model:
		*
		* +-------------------+ +--------------------+ +--------------+
		* + pre_ct (tc chain) +----->+ CT (nat or no nat) +--->+ post_ct +----->
		* + original match + \| + tuple + zone match + \| + fte_id match + \|
		* +-------------------+ \| +--------------------+ \| +--------------+ \|
		* v v v
		* set chain miss mapping set mark original
		* set fte_id set label filter
		* set zone set established actions
		* set tunnel_id do nat (if needed)
		* do decap
		* +---------------------+
		* + fdb prio (tc chain) +
		* + original match +
		* +---------------------+
		* \| set chain miss mapping
		* \| set fte_id
		* \| set tunnel_id
		* \| do decap
		* v
		* +---------------------+
		* + pre_ct/pre_ct_nat + if matches +---------------------+
		* + zone+nat match +---------------->+ post_ct (see below) +
		* +---------------------+ set zone +---------------------+
		* \| set zone
		* v
		* +--------------------+
		* + CT (nat or no nat) +
		* + tuple + zone match +
		* +--------------------+
		* \| set mark
		* \| set label
		* \| set established
		* \| do nat (if needed)
		* v
		* +--------------+
		* + post_ct + original filter actions
		* + fte_id match +------------------------>
		* +--------------+
		*/
		static int
		__mlx5_tc_ct_flow_offload(struct mlx5e_priv *priv,
		@@ -951,14 +1223,6 @@ __mlx5_tc_ct_flow_offload(struct mlx5e_priv *priv,
		goto err_mapping;
		}

		err = mlx5e_tc_match_to_reg_set(esw->dev, &pre_mod_acts, ZONE_TO_REG,
		attr->ct_attr.zone &
		MLX5_CT_ZONE_MASK);
		if (err) {
		ct_dbg("Failed to set zone register mapping");
		goto err_mapping;
		}

		err = mlx5e_tc_match_to_reg_set(esw->dev, &pre_mod_acts,
		FTEID_TO_REG, fte_id);
		if (err) {
		@@ -1018,7 +1282,7 @@ __mlx5_tc_ct_flow_offload(struct mlx5e_priv *priv,

		/* Change original rule point to ct table */
		pre_ct_attr->dest_chain = 0;
		pre_ct_attr->dest_ft = nat ? ct_priv->ct_nat : ct_priv->ct;
		pre_ct_attr->dest_ft = nat ? ft->pre_ct_nat.fdb : ft->pre_ct.fdb;
		ct_flow->pre_ct_rule = mlx5_eswitch_add_offloaded_rule(esw,
		orig_spec,
		pre_ct_attr);

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h

+21 −19

Original line number	Diff line number	Diff line
		@@ -6,25 +6,6 @@

		#include "en.h"

		#define MLX5E_SQ_NOPS_ROOM (MLX5_SEND_WQE_MAX_WQEBBS - 1)
		#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
		MLX5E_SQ_NOPS_ROOM)

		#ifndef CONFIG_MLX5_EN_TLS
		#define MLX5E_SQ_TLS_ROOM (0)
		#else
		/* TLS offload requires additional stop_room for:
		* - a resync SKB.
		* kTLS offload requires fixed additional stop_room for:
		* - a static params WQE, and a progress params WQE.
		* The additional MTU-depending room for the resync DUMP WQEs
		* will be calculated and added in runtime.
		*/
		#define MLX5E_SQ_TLS_ROOM \
		(MLX5_SEND_WQE_MAX_WQEBBS + \
		MLX5E_KTLS_STATIC_WQEBBS + MLX5E_KTLS_PROGRESS_WQEBBS)
		#endif

		#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))

		enum mlx5e_icosq_wqe_type {
		@@ -331,4 +312,25 @@ mlx5e_set_eseg_swp(struct sk_buff skb, struct mlx5_wqe_eth_seg eseg,
		}
		}

		static inline u16 mlx5e_stop_room_for_wqe(u16 wqe_size)
		{
		BUILD_BUG_ON(PAGE_SIZE / MLX5_SEND_WQE_BB < MLX5_SEND_WQE_MAX_WQEBBS);

		/* A WQE must not cross the page boundary, hence two conditions:
		* 1. Its size must not exceed the page size.
		* 2. If the WQE size is X, and the space remaining in a page is less
		* than X, this space needs to be padded with NOPs. So, one WQE of
		* size X may require up to X-1 WQEBBs of padding, which makes the
		* stop room of X-1 + X.
		* WQE size is also limited by the hardware limit.
		*/

		if (__builtin_constant_p(wqe_size))
		BUILD_BUG_ON(wqe_size > MLX5_SEND_WQE_MAX_WQEBBS);
		else
		WARN_ON_ONCE(wqe_size > MLX5_SEND_WQE_MAX_WQEBBS);

		return wqe_size * 2 - 1;
		}

		#endif

drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -257,8 +257,10 @@ enum {
		static int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)
		{
		if (unlikely(!sq->mpwqe.wqe)) {
		const u16 stop_room = mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS);

		if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc,
		MLX5E_XDPSQ_STOP_ROOM))) {
		stop_room))) {
		/* SQ is full, ring doorbell */
		mlx5e_xmit_xdp_doorbell(sq);
		sq->stats->full++;

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