Commit 3f3ab178 authored by Tariq Toukan's avatar Tariq Toukan Committed by Saeed Mahameed
Browse files

net/mlx5e: Take DCBNL-related definitions into dedicated files 



Take DCBNL-related definitions out of the common en.h header,
Use a dedicated header file for exposing them.
Some need not to be exposed, use them locally in the .c file.
Use stubs to eliminate use of CONFIG_MLX5_CORE_EN_DCB in the
generic control flows.

Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 5ffb4d85

drivers/net/ethernet/mellanox/mlx5/core/en.h

+1 −49
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#include "wq.h"

#include "mlx5_core.h"

#include "en_stats.h"

#include "en/dcbnl.h"

#include "en/fs.h"

#include "lib/hv_vhca.h"
@@ -68,8 +69,6 @@ struct page_pool; 
#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))

#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))



#define MLX5E_MAX_PRIORITY      8

#define MLX5E_MAX_DSCP          64

#define MLX5E_MAX_NUM_TC	8



#define MLX5_RX_HEADROOM NET_SKB_PAD
@@ -242,10 +241,6 @@ enum mlx5e_priv_flag { 


#define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))



#ifdef CONFIG_MLX5_CORE_EN_DCB

#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */

#endif



struct mlx5e_params {

	u8  log_sq_size;

	u8  rq_wq_type;
@@ -270,42 +265,6 @@ struct mlx5e_params { 
	int hard_mtu;

};



#ifdef CONFIG_MLX5_CORE_EN_DCB

struct mlx5e_cee_config {

	/* bw pct for priority group */

	u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];

	u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];

	bool                       pfc_setting[CEE_DCBX_MAX_PRIO];

	bool                       pfc_enable;

};



enum {

	MLX5_DCB_CHG_RESET,

	MLX5_DCB_NO_CHG,

	MLX5_DCB_CHG_NO_RESET,

};



struct mlx5e_dcbx {

	enum mlx5_dcbx_oper_mode   mode;

	struct mlx5e_cee_config    cee_cfg; /* pending configuration */

	u8                         dscp_app_cnt;



	/* The only setting that cannot be read from FW */

	u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];

	u8                         cap;



	/* Buffer configuration */

	bool                       manual_buffer;

	u32                        cable_len;

	u32                        xoff;

};



struct mlx5e_dcbx_dp {

	u8                         dscp2prio[MLX5E_MAX_DSCP];

	u8                         trust_state;

};

#endif



enum {

	MLX5E_RQ_STATE_ENABLED,

	MLX5E_RQ_STATE_RECOVERING,
@@ -1068,13 +1027,6 @@ static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 
}



extern const struct ethtool_ops mlx5e_ethtool_ops;

#ifdef CONFIG_MLX5_CORE_EN_DCB

extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;

int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);

void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);

void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);

void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);

#endif



int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,

		     u32 *in);

drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */

/* Copyright (c) 2020 Mellanox Technologies. */



#ifndef __MLX5E_DCBNL_H__

#define __MLX5E_DCBNL_H__



#ifdef CONFIG_MLX5_CORE_EN_DCB



#define MLX5E_MAX_PRIORITY (8)



struct mlx5e_cee_config {

	/* bw pct for priority group */

	u8                         pg_bw_pct[CEE_DCBX_MAX_PGS];

	u8                         prio_to_pg_map[CEE_DCBX_MAX_PRIO];

	bool                       pfc_setting[CEE_DCBX_MAX_PRIO];

	bool                       pfc_enable;

};



struct mlx5e_dcbx {

	enum mlx5_dcbx_oper_mode   mode;

	struct mlx5e_cee_config    cee_cfg; /* pending configuration */

	u8                         dscp_app_cnt;



	/* The only setting that cannot be read from FW */

	u8                         tc_tsa[IEEE_8021QAZ_MAX_TCS];

	u8                         cap;



	/* Buffer configuration */

	bool                       manual_buffer;

	u32                        cable_len;

	u32                        xoff;

};



#define MLX5E_MAX_DSCP (64)



struct mlx5e_dcbx_dp {

	u8                         dscp2prio[MLX5E_MAX_DSCP];

	u8                         trust_state;

};



void mlx5e_dcbnl_build_netdev(struct net_device *netdev);

void mlx5e_dcbnl_build_rep_netdev(struct net_device *netdev);

void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);

void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);

void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);

#else

static inline void mlx5e_dcbnl_build_netdev(struct net_device *netdev) {}

static inline void mlx5e_dcbnl_build_rep_netdev(struct net_device *netdev) {}

static inline void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv) {}

static inline void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv) {}

static inline void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv) {}

#endif



#endif /* __MLX5E_DCBNL_H__ */

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c

+27 −1
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ 
#include "en/port.h"

#include "en/port_buffer.h"



#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */



#define MLX5E_100MB (100000)

#define MLX5E_1GB   (1000000)
@@ -49,6 +51,12 @@ enum { 
	MLX5E_LOWEST_PRIO_GROUP   = 0,

};



enum {

	MLX5_DCB_CHG_RESET,

	MLX5_DCB_NO_CHG,

	MLX5_DCB_CHG_NO_RESET,

};



#define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg)  && \

				   MLX5_CAP_QCAM_REG(mdev, qpts) && \

				   MLX5_CAP_QCAM_REG(mdev, qpdpm))
@@ -238,7 +246,7 @@ static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw, 
 *   Report both group #0 and #1 as ETS type.

 *     All the tcs in group #0 will be reported with 0% BW.

 */

int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)

static int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)

{

	struct mlx5_core_dev *mdev = priv->mdev;

	u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
@@ -1009,6 +1017,24 @@ const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = { 
	.setpfcstate    = mlx5e_dcbnl_setpfcstate,

};



void mlx5e_dcbnl_build_netdev(struct net_device *netdev)

{

	struct mlx5e_priv *priv = netdev_priv(netdev);

	struct mlx5_core_dev *mdev = priv->mdev;



	if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))

		netdev->dcbnl_ops = &mlx5e_dcbnl_ops;

}



void mlx5e_dcbnl_build_rep_netdev(struct net_device *netdev)

{

	struct mlx5e_priv *priv = netdev_priv(netdev);

	struct mlx5_core_dev *mdev = priv->mdev;



	if (MLX5_CAP_GEN(mdev, qos))

		netdev->dcbnl_ops = &mlx5e_dcbnl_ops;

}



static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,

					enum mlx5_dcbx_oper_mode *mode)

{

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+1 −15
Original line number Diff line number Diff line
@@ -66,7 +66,6 @@ 
#include "en/devlink.h"

#include "lib/mlx5.h"





bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)

{

	bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
@@ -4927,10 +4926,7 @@ static void mlx5e_build_nic_netdev(struct net_device *netdev) 


	netdev->netdev_ops = &mlx5e_netdev_ops;



#ifdef CONFIG_MLX5_CORE_EN_DCB

	if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))

		netdev->dcbnl_ops = &mlx5e_dcbnl_ops;

#endif

	mlx5e_dcbnl_build_netdev(netdev);



	netdev->watchdog_timeo    = 15 * HZ;
@@ -5218,9 +5214,7 @@ static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) 
		return err;

	}



#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_initialize(priv);

#endif

	return 0;

}
@@ -5247,9 +5241,7 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv) 
	mlx5e_hv_vhca_stats_create(priv);

	if (netdev->reg_state != NETREG_REGISTERED)

		return;

#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_init_app(priv);

#endif



	queue_work(priv->wq, &priv->set_rx_mode_work);
@@ -5264,10 +5256,8 @@ static void mlx5e_nic_disable(struct mlx5e_priv *priv) 
{

	struct mlx5_core_dev *mdev = priv->mdev;



#ifdef CONFIG_MLX5_CORE_EN_DCB

	if (priv->netdev->reg_state == NETREG_REGISTERED)

		mlx5e_dcbnl_delete_app(priv);

#endif



	rtnl_lock();

	if (netif_running(priv->netdev))
@@ -5564,9 +5554,7 @@ static void *mlx5e_add(struct mlx5_core_dev *mdev) 


	mlx5e_devlink_port_type_eth_set(priv);



#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_init_app(priv);

#endif

	return priv;



err_devlink_port_unregister:
@@ -5589,9 +5577,7 @@ static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) 
	}

#endif

	priv = vpriv;

#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_delete_app(priv);

#endif

	unregister_netdev(priv->netdev);

	mlx5e_devlink_port_unregister(priv);

	mlx5e_detach(mdev, vpriv);

drivers/net/ethernet/mellanox/mlx5/core/en_rep.c

+1 −8
Original line number Diff line number Diff line
@@ -1544,10 +1544,7 @@ static void mlx5e_build_rep_netdev(struct net_device *netdev) 
		/* we want a persistent mac for the uplink rep */

		mlx5_query_mac_address(mdev, netdev->dev_addr);

		netdev->ethtool_ops = &mlx5e_uplink_rep_ethtool_ops;

#ifdef CONFIG_MLX5_CORE_EN_DCB

		if (MLX5_CAP_GEN(mdev, qos))

			netdev->dcbnl_ops = &mlx5e_dcbnl_ops;

#endif

		mlx5e_dcbnl_build_rep_netdev(netdev);

	} else {

		netdev->netdev_ops = &mlx5e_netdev_ops_rep;

		eth_hw_addr_random(netdev);
@@ -1929,10 +1926,8 @@ static void mlx5e_uplink_rep_enable(struct mlx5e_priv *priv) 
	mlx5_lag_add(mdev, netdev);

	priv->events_nb.notifier_call = uplink_rep_async_event;

	mlx5_notifier_register(mdev, &priv->events_nb);

#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_initialize(priv);

	mlx5e_dcbnl_init_app(priv);

#endif

}



static void mlx5e_uplink_rep_disable(struct mlx5e_priv *priv)
@@ -1940,9 +1935,7 @@ static void mlx5e_uplink_rep_disable(struct mlx5e_priv *priv) 
	struct mlx5_core_dev *mdev = priv->mdev;

	struct mlx5e_rep_priv *rpriv = priv->ppriv;



#ifdef CONFIG_MLX5_CORE_EN_DCB

	mlx5e_dcbnl_delete_app(priv);

#endif

	mlx5_notifier_unregister(mdev, &priv->events_nb);

	cancel_work_sync(&rpriv->uplink_priv.reoffload_flows_work);

	mlx5_lag_remove(mdev);

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