Commit ea21768a authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sunxi-dt-for-5.5-2' of... 

Merge tag 'sunxi-dt-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

A few more DT patches for 5.5, mostly:
  - USB3 support for the H6
  - Deinterlacer support for the H3
  - eDP Bridge support on the Teres-I
  - More DT cleanups thanks to the validation

* tag 'sunxi-dt-for-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: h6: Remove useless reset name
  ARM: dts: sun6i: Remove useless reset-names
  arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host support
  arm64: dts: allwinner: h6: add USB3 device nodes
  dt-bindings: Add ANX6345 DP/eDP transmitter binding
  arm64: dts: allwinner: a64: enable ANX6345 bridge on Teres-I
  dts: arm: sun8i: h3: Enable deinterlace unit
  ARM: dts: sunxi: h3/h5: Add MBUS controller node
  dt-bindings: bus: sunxi: Add H3 MBUS compatible

Link: https://lore.kernel.org/r/58ad00a8-9579-4811-969a-a74e331ee9a2.lettre@localhost


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f129230b 74ab6d9d

Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ bus. 
Required properties:

 - compatible: Must be one of:

	- allwinner,sun5i-a13-mbus

	- allwinner,sun8i-h3-mbus

 - reg: Offset and length of the register set for the controller

 - clocks: phandle to the clock driving the controller

 - dma-ranges: See section 2.3.9 of the DeviceTree Specification

Documentation/devicetree/bindings/display/bridge/anx6345.yaml

0 → 100644
+102 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Analogix ANX6345 eDP Transmitter Device Tree Bindings



maintainers:

  - Torsten Duwe <duwe@lst.de>



description: |

  The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for

  portable devices.



properties:

  compatible:

    const: analogix,anx6345



  reg:

    maxItems: 1

    description: base I2C address of the device



  reset-gpios:

    maxItems: 1

    description: GPIO connected to active low reset



  dvdd12-supply:

    maxItems: 1

    description: Regulator for 1.2V digital core power.



  dvdd25-supply:

    maxItems: 1

    description: Regulator for 2.5V digital core power.



  ports:

    type: object



    properties:

      port@0:

        type: object

        description: |

          Video port for LVTTL input



      port@1:

        type: object

        description: |

          Video port for eDP output (panel or connector).

          May be omitted if EDID works reliably.



    required:

      - port@0



required:

  - compatible

  - reg

  - reset-gpios

  - dvdd12-supply

  - dvdd25-supply

  - ports



additionalProperties: false



examples:

  - |

    i2c0 {

      #address-cells = <1>;

      #size-cells = <0>;



      anx6345: anx6345@38 {

        compatible = "analogix,anx6345";

        reg = <0x38>;

        reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>;

        dvdd25-supply = <&reg_dldo2>;

        dvdd12-supply = <&reg_fldo1>;



        ports {

          #address-cells = <1>;

          #size-cells = <0>;



          anx6345_in: port@0 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <0>;

            anx6345_in_tcon0: endpoint@0 {

              reg = <0>;

              remote-endpoint = <&tcon0_out_anx6345>;

            };

          };



          anx6345_out: port@1 {

            #address-cells = <1>;

            #size-cells = <0>;

            reg = <1>;

            anx6345_out_panel: endpoint@0 {

              reg = <0>;

              remote-endpoint = <&panel_in_edp>;

            };

          };

        };

      };

    };

arch/arm/boot/dts/sun6i-a31.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -469,7 +469,6 @@ 
				 <&ccu CLK_PLL_VIDEO1_2X>;

			clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";

			resets = <&ccu RST_AHB1_HDMI>;

			reset-names = "ahb";

			dma-names = "ddc-tx", "ddc-rx", "audio-tx";

			dmas = <&dma 13>, <&dma 13>, <&dma 14>;

			status = "disabled";

arch/arm/boot/dts/sun8i-h3.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -120,6 +120,19 @@ 
	};



	soc {

		deinterlace: deinterlace@1400000 {

			compatible = "allwinner,sun8i-h3-deinterlace";

			reg = <0x01400000 0x20000>;

			clocks = <&ccu CLK_BUS_DEINTERLACE>,

				 <&ccu CLK_DEINTERLACE>,

				 <&ccu CLK_DRAM_DEINTERLACE>;

			clock-names = "bus", "mod", "ram";

			resets = <&ccu RST_BUS_DEINTERLACE>;

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;

			interconnects = <&mbus 9>;

			interconnect-names = "dma-mem";

		};



		syscon: system-control@1c00000 {

			compatible = "allwinner,sun8i-h3-system-control";

			reg = <0x01c00000 0x1000>;

arch/arm/boot/dts/sunxi-h3-h5.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ 
		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		dma-ranges;

		ranges;



		display_clocks: clock@1000000 {
@@ -543,6 +544,14 @@ 
			};

		};



		mbus: dram-controller@1c62000 {

			compatible = "allwinner,sun8i-h3-mbus";

			reg = <0x01c62000 0x1000>;

			clocks = <&ccu 113>;

			dma-ranges = <0x00000000 0x40000000 0xc0000000>;

			#interconnect-cells = <1>;

		};



		spi0: spi@1c68000 {

			compatible = "allwinner,sun8i-h3-spi";

			reg = <0x01c68000 0x1000>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE