arm/arm64: gic-v3: Add PMR and RPR accessors (e99da7c6) · Commits · 戴 / test

arch/arm/include/asm/arch_gicv3.h

+16 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,7 @@
		#define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5)
		#define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7)
		#define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3)
		#define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3)

		#define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 \| x)
		#define ICC_AP0R0 __ICC_AP0Rx(0)
		@@ -245,6 +246,21 @@ static inline void gic_write_bpr1(u32 val)
		write_sysreg(val, ICC_BPR1);
		}

		static inline u32 gic_read_pmr(void)
		{
		return read_sysreg(ICC_PMR);
		}

		static inline void gic_write_pmr(u32 val)
		{
		write_sysreg(val, ICC_PMR);
		}

		static inline u32 gic_read_rpr(void)
		{
		return read_sysreg(ICC_RPR);
		}

		/*
		* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
		* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't

+15 −0

Original line number	Diff line number	Diff line
		@@ -114,6 +114,21 @@ static inline void gic_write_bpr1(u32 val)
		write_sysreg_s(val, SYS_ICC_BPR1_EL1);
		}

		static inline u32 gic_read_pmr(void)
		{
		return read_sysreg_s(SYS_ICC_PMR_EL1);
		}

		static inline void gic_write_pmr(u32 val)
		{
		write_sysreg_s(val, SYS_ICC_PMR_EL1);
		}

		static inline u32 gic_read_rpr(void)
		{
		return read_sysreg_s(SYS_ICC_RPR_EL1);
		}

		#define gic_read_typer(c) readq_relaxed(c)
		#define gic_write_irouter(v, c) writeq_relaxed(v, c)
		#define gic_read_lpir(c) readq_relaxed(c)