Commit e8e35c62 authored Jan 24, 2020 by Akhil P Oommen Committed by Rob Clark Feb 11, 2020

drm/msm/a6xx: Correct the highestbank configuration



Highest bank bit configuration is different for a618 gpu. Update
it with the correct configuration which is the reset value incidentally.

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Fixes: e812744c ("drm: msm: a6xx: Add support for A618")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>

parent e4f9bbe9

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+6 −4

Original line number	Diff line number	Diff line
		@@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
		/* Select CP0 to always count cycles */
		gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);

		if (adreno_is_a630(adreno_gpu)) {
		gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
		gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
		gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
		gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
		}

		/* Enable fault detection */
		gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,

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