msm:disp:dpu1: add UBWC support for display on SC7180 (e4f9bbe9) · Commits · 戴 / test

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

+57 −1

Original line number	Diff line number	Diff line
		@@ -12,6 +12,7 @@

		#define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base)

		#define HW_REV 0x0
		#define HW_INTR_STATUS 0x0010

		/* Max BW defined in KBps */
		@@ -22,6 +23,17 @@ struct dpu_irq_controller {
		struct irq_domain *domain;
		};

		struct dpu_hw_cfg {
		u32 val;
		u32 offset;
		};

		struct dpu_mdss_hw_init_handler {
		u32 hw_rev;
		u32 hw_reg_count;
		struct dpu_hw_cfg* hw_cfg;
		};

		struct dpu_mdss {
		struct msm_mdss base;
		void __iomem *mmio;
		@@ -32,6 +44,44 @@ struct dpu_mdss {
		u32 num_paths;
		};

		static struct dpu_hw_cfg hw_cfg[] = {
		{
		/* UBWC global settings */
		.val = 0x1E,
		.offset = 0x144,
		}
		};

		static struct dpu_mdss_hw_init_handler cfg_handler[] = {
		{ .hw_rev = DPU_HW_VER_620,
		.hw_reg_count = ARRAY_SIZE(hw_cfg),
		.hw_cfg = hw_cfg
		},
		};

		static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev)
		{
		int i;
		u32 count = 0;
		struct dpu_hw_cfg *hw_cfg = NULL;

		for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
		if (cfg_handler[i].hw_rev == hw_rev) {
		hw_cfg = cfg_handler[i].hw_cfg;
		count = cfg_handler[i].hw_reg_count;
		break;
		}
		}

		for (i = 0; i < count; i++ ) {
		writel_relaxed(hw_cfg->val,
		dpu_mdss->mmio + hw_cfg->offset);
		hw_cfg++;
		}

		return;
		}

		static int dpu_mdss_parse_data_bus_icc_path(struct drm_device *dev,
		struct dpu_mdss *dpu_mdss)
		{
		@@ -174,12 +224,18 @@ static int dpu_mdss_enable(struct msm_mdss *mdss)
		struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss);
		struct dss_module_power *mp = &dpu_mdss->mp;
		int ret;
		u32 mdss_rev;

		dpu_mdss_icc_request_bw(mdss);

		ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true);
		if (ret)
		if (ret) {
		DPU_ERROR("clock enable failed, ret:%d\n", ret);
		return ret;
		}

		mdss_rev = readl_relaxed(dpu_mdss->mmio + HW_REV);
		dpu_mdss_hw_init(dpu_mdss, mdss_rev);

		return ret;
		}

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