Commit e66796b9 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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ARM: dts: r8a7792: add [H]SCIF support 



Describe [H]SCIFs in the R8A7792 device tree.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent fdf8ec0a

arch/arm/boot/dts/r8a7792.dtsi

+90 −0
Original line number Diff line number Diff line
@@ -143,6 +143,96 @@ 
			dma-channels = <15>;

		};



		scif0: serial@e6e60000 {

			compatible = "renesas,scif-r8a7792",

				     "renesas,rcar-gen2-scif", "renesas,scif";

			reg = <0 0xe6e60000 0 64>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,

			       <&dmac1 0x29>, <&dmac1 0x2a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			compatible = "renesas,scif-r8a7792",

				     "renesas,rcar-gen2-scif", "renesas,scif";

			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,

			       <&dmac1 0x2d>, <&dmac1 0x2e>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		scif2: serial@e6e58000 {

			compatible = "renesas,scif-r8a7792",

				     "renesas,rcar-gen2-scif", "renesas,scif";

			reg = <0 0xe6e58000 0 64>;

			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,

			       <&dmac1 0x2b>, <&dmac1 0x2c>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		scif3: serial@e6ea8000 {

			compatible = "renesas,scif-r8a7792",

				     "renesas,rcar-gen2-scif", "renesas,scif";

			reg = <0 0xe6ea8000 0 64>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,

			       <&dmac1 0x2f>, <&dmac1 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		hscif0: serial@e62c0000 {

			compatible = "renesas,hscif-r8a7792",

				     "renesas,rcar-gen2-hscif", "renesas,hscif";

			reg = <0 0xe62c0000 0 96>;

			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,

			       <&dmac1 0x39>, <&dmac1 0x3a>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		hscif1: serial@e62c8000 {

			compatible = "renesas,hscif-r8a7792",

				     "renesas,rcar-gen2-hscif", "renesas,hscif";

			reg = <0 0xe62c8000 0 96>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,

			       <&dmac1 0x4d>, <&dmac1 0x4e>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;

			status = "disabled";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@e6150000 {

			compatible = "renesas,r8a7792-cpg-clocks",

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