Commit e5abaab3 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() 



Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.

v2: Remember the gvt

Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201028213323.5423-9-ville.syrjala@linux.intel.com
parent 8625b221

drivers/gpu/drm/i915/gvt/display.c

+7 −7
Original line number Diff line number Diff line
@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 


	if (IS_BROXTON(dev_priv)) {

		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=

			~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |

			  BXT_DE_PORT_HP_DDI(HPD_PORT_B) |

			  BXT_DE_PORT_HP_DDI(HPD_PORT_C));

			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |

			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |

			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDI(HPD_PORT_A);

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

		}



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDI(HPD_PORT_B);

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);

		}



		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				BXT_DE_PORT_HP_DDI(HPD_PORT_C);

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);

		}



		return;
@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

		if (IS_BROADWELL(dev_priv))

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_PORT_DP_A_HOTPLUG;

				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);

		else

			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

drivers/gpu/drm/i915/i915_irq.c

+9 −9
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = { 
};



static const u32 hpd_bdw[HPD_NUM_PINS] = {

	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,

	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),

};



static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = { 
};



static const u32 hpd_bxt[HPD_NUM_PINS] = {

	[HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),

	[HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),

	[HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),

	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),

	[HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),

	[HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),

};



static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2379,7 +2379,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) 
					found = true;

				}

			} else if (IS_BROADWELL(dev_priv)) {

				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;

				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;

				if (tmp_mask) {

					ilk_hpd_irq_handler(dev_priv, tmp_mask);

					found = true;
@@ -3420,13 +3420,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, 
	 * For BXT invert bit has to be set based on AOB design

	 * for HPD detection logic, update it based on VBT fields.

	 */

	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&

	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&

	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))

		hotplug |= BXT_DDIA_HPD_INVERT;

	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&

	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&

	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))

		hotplug |= BXT_DDIB_HPD_INVERT;

	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&

	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&

	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))

		hotplug |= BXT_DDIC_HPD_INVERT;
@@ -3595,7 +3595,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 
	if (IS_GEN9_LP(dev_priv))

		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;

	else if (IS_BROADWELL(dev_priv))

		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;

		de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;



	if (INTEL_GEN(dev_priv) >= 12) {

		enum transcoder trans;

drivers/gpu/drm/i915/i915_reg.h

+5 −5
Original line number Diff line number Diff line
@@ -7828,11 +7828,11 @@ enum { 
#define  GEN9_AUX_CHANNEL_B		(1 << 25)

#define  DSI1_TE			(1 << 24)

#define  DSI0_TE			(1 << 23)

#define  BXT_DE_PORT_HP_DDI(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))

#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \

					 BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \

					 BXT_DE_PORT_HP_DDI(HPD_PORT_C))

#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)

#define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))

#define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \

					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \

					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))

#define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)

#define  BXT_DE_PORT_GMBUS		(1 << 1)

#define  GEN8_AUX_CHANNEL_A		(1 << 0)

#define  TGL_DE_PORT_AUX_USBC6		(1 << 13)

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